The Experts below are selected from a list of 153477 Experts worldwide ranked by ideXlab platform
Raghuram S. Tupuri - One of the best experts on this subject based on the ideXlab platform.
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VLSI Design - A Robust Top-Down Dynamic Power Estimation Methodology for Delay Constrained Register Transfer Level Sequential Circuits
21st International Conference on VLSI Design (VLSID 2008), 2008Co-Authors: Sriram Sambamurthy, Jacob A. Abraham, Raghuram S. TupuriAbstract:We present a top-down dynamic Power Estimation methodology for delay constrained sequential circuits. The methodology works at the register transfer level (RT-Level), and applies to both structural and behavioral descriptions of circuits. The average Power consumption of a circuit varies with the worst case cycle-time or frequency of operation. As the cycle-time is reduced, the increase in the capacitance of the circuit due to technology mapping and optimization is captured by our technique at the RT-Level using the principles of logical effort. Switching activity is obtained at the RT-Level visible nodes through RT-Level functional simulation. This information is utilized to approximate the activities at the remaining nodes of the circuit and combined with capacitance to estimate dynamic Power. Power Estimation results for RT-Level sequential circuits indicate good accuracy (average error
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Delay Constrained Register Transfer Level Dynamic Power Estimation
Lecture Notes in Computer Science, 2006Co-Authors: Sriram Sambamurthy, Jacob A. Abraham, Raghuram S. TupuriAbstract:We present a top-down technique to estimate the average dynamic Power consumption of combinational circuits at the register transfer level. The technique also captures the Power-delay characteristics of a given combinational circuit. It uses the principles of logical effort to estimate the variation in capacitance, and a combination of existing techniques to estimate the variation in activity, over the delay curve of operation of the circuit. The technique does not involve post-Estimation characterization and is applicable across technology nodes. The estimated Power obtained from our method shows good accuracy with respect to the Power obtained from a commercial gate-level Power Estimation tool.
Sriram Sambamurthy - One of the best experts on this subject based on the ideXlab platform.
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VLSI Design - A Robust Top-Down Dynamic Power Estimation Methodology for Delay Constrained Register Transfer Level Sequential Circuits
21st International Conference on VLSI Design (VLSID 2008), 2008Co-Authors: Sriram Sambamurthy, Jacob A. Abraham, Raghuram S. TupuriAbstract:We present a top-down dynamic Power Estimation methodology for delay constrained sequential circuits. The methodology works at the register transfer level (RT-Level), and applies to both structural and behavioral descriptions of circuits. The average Power consumption of a circuit varies with the worst case cycle-time or frequency of operation. As the cycle-time is reduced, the increase in the capacitance of the circuit due to technology mapping and optimization is captured by our technique at the RT-Level using the principles of logical effort. Switching activity is obtained at the RT-Level visible nodes through RT-Level functional simulation. This information is utilized to approximate the activities at the remaining nodes of the circuit and combined with capacitance to estimate dynamic Power. Power Estimation results for RT-Level sequential circuits indicate good accuracy (average error
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Delay Constrained Register Transfer Level Dynamic Power Estimation
Lecture Notes in Computer Science, 2006Co-Authors: Sriram Sambamurthy, Jacob A. Abraham, Raghuram S. TupuriAbstract:We present a top-down technique to estimate the average dynamic Power consumption of combinational circuits at the register transfer level. The technique also captures the Power-delay characteristics of a given combinational circuit. It uses the principles of logical effort to estimate the variation in capacitance, and a combination of existing techniques to estimate the variation in activity, over the delay curve of operation of the circuit. The technique does not involve post-Estimation characterization and is applicable across technology nodes. The estimated Power obtained from our method shows good accuracy with respect to the Power obtained from a commercial gate-level Power Estimation tool.
Srinivas Devadas - One of the best experts on this subject based on the ideXlab platform.
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Power Estimation Under User-Specified Input Sequences and Programs
Integrated Computer-Aided Engineering, 1998Co-Authors: Jose Monteiro, Srinivas DevadasAbstract:We describe an approach to estimate the average Power dissipation in sequential logic circuits under user-specified input sequences or programs. This approach will aid the design of programmable controllers or processors, by enabling the Estimation of the Power dissipated when the controller or processor is running specific application programs. Current approaches to sequential circuit Power Estimation are limited by the fact that the input sequences to the sequential circuit are assumed to be uncorrelated. In reality, the inputs come from other sequential circuits, or are application programs. In this paper we show how user-specified sequences and programs can be modeled using a finite state machine, termed an input-modeling finite state machines or IMFSM. Power Estimation can be carried out using existing sequential circuit Power Estimation methods on a cascade circuit consisting of the IMFSM and the original sequential circuit.
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Power Estimation for Sequential Circuits
Computer-Aided Design Techniques for Low Power Sequential Logic Circuits, 1997Co-Authors: Jose Monteiro, Srinivas DevadasAbstract:The Power Estimation methods described in the previous chapters apply to combinational logic blocks. In this chapter we describe techniques that target issues particular to sequential circuits.
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Techniques for Power Estimation and optimization at the logic level: A survey
Journal of VLSI signal processing systems for signal image and video technology, 1996Co-Authors: Jose Monteiro, Srinivas DevadasAbstract:We present a survey of state-of-the-art Power Estimation methods and optimization techniques targeting low Power VLSI circuits. Estimation and optimizations at the circuit and logic levels are considered.
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techniques for the Power Estimation of sequential logic circuits under user specified input sequences and programs
International Symposium on Low Power Electronics and Design, 1995Co-Authors: Jose Monteiro, Srinivas DevadasAbstract:We describe an approach to estimate the average Power dissipation in sequential logic circuits under user-specified input sequences or programs. This approach will aid the design of programmable controllers or processors, by enabling the Estimation of the Power dissipated when the controller or processor is running specific application programs. Current approaches to sequential circuit Power Estimation are limited by the fact that the input sequences to the sequential circuit are assumed to be uncorrelated. In reality, the inputs come from other sequential circuits, or are application programs. In this paper we show how user-specified sequences and programs can be modeled using a finite state machine, termed an input-modeling finite state machines or IMFSM. Power Estimation can be carried out using existing sequential circuit Power Estimation methods on a cascade circuit consisting of the IMFSM and the original sequential circuit.
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ISLPD - Techniques for the Power Estimation of sequential logic circuits under user-specified input sequences and programs
Proceedings of the 1995 international symposium on Low power design - ISLPED '95, 1995Co-Authors: Jose Monteiro, Srinivas DevadasAbstract:We describe an approach to estimate the average Power dissipation in sequential logic circuits under user-specified input sequences or programs. This approach will aid the design of programmable controllers or processors, by enabling the Estimation of the Power dissipated when the controller or processor is running specific application programs. Current approaches to sequential circuit Power Estimation are limited by the fact that the input sequences to the sequential circuit are assumed to be uncorrelated. In reality, the inputs come from other sequential circuits, or are application programs. In this paper we show how user-specified sequences and programs can be modeled using a finite state machine, termed an input-modeling finite state machines or IMFSM. Power Estimation can be carried out using existing sequential circuit Power Estimation methods on a cascade circuit consisting of the IMFSM and the original sequential circuit.
Jacob A. Abraham - One of the best experts on this subject based on the ideXlab platform.
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VLSI Design - A Robust Top-Down Dynamic Power Estimation Methodology for Delay Constrained Register Transfer Level Sequential Circuits
21st International Conference on VLSI Design (VLSID 2008), 2008Co-Authors: Sriram Sambamurthy, Jacob A. Abraham, Raghuram S. TupuriAbstract:We present a top-down dynamic Power Estimation methodology for delay constrained sequential circuits. The methodology works at the register transfer level (RT-Level), and applies to both structural and behavioral descriptions of circuits. The average Power consumption of a circuit varies with the worst case cycle-time or frequency of operation. As the cycle-time is reduced, the increase in the capacitance of the circuit due to technology mapping and optimization is captured by our technique at the RT-Level using the principles of logical effort. Switching activity is obtained at the RT-Level visible nodes through RT-Level functional simulation. This information is utilized to approximate the activities at the remaining nodes of the circuit and combined with capacitance to estimate dynamic Power. Power Estimation results for RT-Level sequential circuits indicate good accuracy (average error
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Delay Constrained Register Transfer Level Dynamic Power Estimation
Lecture Notes in Computer Science, 2006Co-Authors: Sriram Sambamurthy, Jacob A. Abraham, Raghuram S. TupuriAbstract:We present a top-down technique to estimate the average dynamic Power consumption of combinational circuits at the register transfer level. The technique also captures the Power-delay characteristics of a given combinational circuit. It uses the principles of logical effort to estimate the variation in capacitance, and a combination of existing techniques to estimate the variation in activity, over the delay curve of operation of the circuit. The technique does not involve post-Estimation characterization and is applicable across technology nodes. The estimated Power obtained from our method shows good accuracy with respect to the Power obtained from a commercial gate-level Power Estimation tool.
Jose Monteiro - One of the best experts on this subject based on the ideXlab platform.
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Power Estimation Under User-Specified Input Sequences and Programs
Integrated Computer-Aided Engineering, 1998Co-Authors: Jose Monteiro, Srinivas DevadasAbstract:We describe an approach to estimate the average Power dissipation in sequential logic circuits under user-specified input sequences or programs. This approach will aid the design of programmable controllers or processors, by enabling the Estimation of the Power dissipated when the controller or processor is running specific application programs. Current approaches to sequential circuit Power Estimation are limited by the fact that the input sequences to the sequential circuit are assumed to be uncorrelated. In reality, the inputs come from other sequential circuits, or are application programs. In this paper we show how user-specified sequences and programs can be modeled using a finite state machine, termed an input-modeling finite state machines or IMFSM. Power Estimation can be carried out using existing sequential circuit Power Estimation methods on a cascade circuit consisting of the IMFSM and the original sequential circuit.
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Power Estimation for Sequential Circuits
Computer-Aided Design Techniques for Low Power Sequential Logic Circuits, 1997Co-Authors: Jose Monteiro, Srinivas DevadasAbstract:The Power Estimation methods described in the previous chapters apply to combinational logic blocks. In this chapter we describe techniques that target issues particular to sequential circuits.
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Techniques for Power Estimation and optimization at the logic level: A survey
Journal of VLSI signal processing systems for signal image and video technology, 1996Co-Authors: Jose Monteiro, Srinivas DevadasAbstract:We present a survey of state-of-the-art Power Estimation methods and optimization techniques targeting low Power VLSI circuits. Estimation and optimizations at the circuit and logic levels are considered.
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techniques for the Power Estimation of sequential logic circuits under user specified input sequences and programs
International Symposium on Low Power Electronics and Design, 1995Co-Authors: Jose Monteiro, Srinivas DevadasAbstract:We describe an approach to estimate the average Power dissipation in sequential logic circuits under user-specified input sequences or programs. This approach will aid the design of programmable controllers or processors, by enabling the Estimation of the Power dissipated when the controller or processor is running specific application programs. Current approaches to sequential circuit Power Estimation are limited by the fact that the input sequences to the sequential circuit are assumed to be uncorrelated. In reality, the inputs come from other sequential circuits, or are application programs. In this paper we show how user-specified sequences and programs can be modeled using a finite state machine, termed an input-modeling finite state machines or IMFSM. Power Estimation can be carried out using existing sequential circuit Power Estimation methods on a cascade circuit consisting of the IMFSM and the original sequential circuit.
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ISLPD - Techniques for the Power Estimation of sequential logic circuits under user-specified input sequences and programs
Proceedings of the 1995 international symposium on Low power design - ISLPED '95, 1995Co-Authors: Jose Monteiro, Srinivas DevadasAbstract:We describe an approach to estimate the average Power dissipation in sequential logic circuits under user-specified input sequences or programs. This approach will aid the design of programmable controllers or processors, by enabling the Estimation of the Power dissipated when the controller or processor is running specific application programs. Current approaches to sequential circuit Power Estimation are limited by the fact that the input sequences to the sequential circuit are assumed to be uncorrelated. In reality, the inputs come from other sequential circuits, or are application programs. In this paper we show how user-specified sequences and programs can be modeled using a finite state machine, termed an input-modeling finite state machines or IMFSM. Power Estimation can be carried out using existing sequential circuit Power Estimation methods on a cascade circuit consisting of the IMFSM and the original sequential circuit.
