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Ka Nang Leung - One of the best experts on this subject based on the ideXlab platform.
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a full Load hybrid compensated ldo with output capacitance range of 0 to 1 μf
International Conference on Electron Devices and Solid-State Circuits, 2017Co-Authors: Yuet Ho Woo, Kai Ho Mak, Ka Nang LeungAbstract:A full-Load low-dropout regulator (LDO) based on proposed hybrid compensation structure is proposed. The proposed LDO makes use of an NMOSFET power transistor. The LDO is able to be stabilized for 0 to 1-μF Capacitive Load. Experimental results prove the LDO stability and fast recovery speed.
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A Two-Stage Large-Capacitive-Load Amplifier With Multiple Cross-Coupled Small-Gain Stages
IEEE Transactions on Very Large Scale Integration Systems, 2016Co-Authors: Marco Ho, Hiu Ching Poon, Shi Bu, Ka Nang LeungAbstract:A two-stage large-Capacitive-Load amplifier with multiple cross-coupled small-gain stages is proposed in this paper. The cross-coupled structure of the small-gain stages augments the large-signal responses, providing significant improvement in the effective output-stage transconductance and, hence, the gain–bandwidth product (GBW). Implemented in a standard 0.13- $\mu \text{m}$ CMOS technology and powered by a 0.7 V supply with a current consumption of $20~\mu \text{A}$ , the proposed amplifier achieves the GBW of 1.17 MHz and the phase margin of 74.8° while driving a Capacitive Load of 9.5 nF. The average slew rate is 0.3679 V/ $\mu \text{s}$ . The on-chip compensation capacitor is only 1.62 pF. The active chip area is 0.0056 mm2.
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a signal and transient current boosting amplifier for large Capacitive Load applications
IEEE Transactions on Circuits and Systems, 2014Co-Authors: Kai Ho Mak, Ka Nang LeungAbstract:A signal- and transient-current boosting (STCB) circuit is proposed and applied to a single-stage amplifier driving large Capacitive Loads. The proposed STCB circuit provides gain-bandwidth product (GBW) extension, slew-rate (SR) improvement and gain enhancement to the amplifier, with only slight alterations to the frequency response and transient response of the single-stage amplifier driving large Capacitive Loads. No on-chip capacitor or resistor is required. The STCB amplifier is fabricated in a commercial 0.18-μm CMOS technology. The active chip area is 0.00705 mm 2 . The supply is 1.8 V, and the current consumption is 20.3 μA. The Capacitive Load (C O ) ranges from about 4.4 nF to 19 nF. The measured results with a ~ 19-nF Load show the small-signal figure-of-merit (FOMS=GBW·C O /power) and the large-signal figure-of-merit (FOML=SR·C O /power) are 150345 MHz · pF/mW and 31213 V/μs·pF/mW, respectively, which correspond to improvements of 1.52 times and 1.36 times, respectively, to the prior art. The achieved phase margin and gain margin are 80.8 ° and 36.3 dB, respectively.
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three stage large Capacitive Load amplifier with damping factor control frequency compensation
IEEE Journal of Solid-state Circuits, 2000Co-Authors: Ka Nang Leung, Wing Hung KiAbstract:A novel damping-factor-control frequency compensation (DFCFC) technique is presented in this paper with detailed theoretical analysis, This compensation technique improves frequency response, transient response, and power supply rejection for amplifiers, especially when driving large Capacitive Loads, Moreover, the required compensation capacitors are small and can be easily integrated in commercial CMOS process. Amplifiers using DFCPC and nested Miller compensation (NMC) driving two Capacitive Loads, 100 and 1000 pF, were fabricated using a 0.8-/spl mu/m CMOS process with V/sub tn/=0.72 V and V/sub tp/=-0.75 V. For the DFCFC amplifier driving a 1000-pF Load, a 1-MHz gain-bandwidth product, 51/spl deg/ phase margin, 0.33-V//spl mu/s slew rate, 3.54-/spl mu/s settling time, and 426-/spl mu/W power consumption are obtained with integrated compensation capacitors. Compared to the NMC amplifier, the frequency and transient responses of the DFCFC amplifier are improved by one order of magnitude with insignificant increase of the power consumption.
Wing Hung Ki - One of the best experts on this subject based on the ideXlab platform.
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a cascode miller compensated three stage amplifier with local impedance attenuation for optimized complex pole control
IEEE Journal of Solid-state Circuits, 2015Co-Authors: Wing Hung KiAbstract:This work presents a power- and area-efficient three-stage amplifier that is able to drive a large Capacitive Load. Removing the inner Miller capacitor and employing cascode Miller compensation in the outer compensation loop could extend the complex-pole frequency of a three-stage amplifier, but result in a high Q-factor. A local impedance attenuation block consisting of a series RC network is proposed to control the complex poles. This block attenuates the high-frequency resistance at the second-stage output and achieves an optimized tradeoff between the frequency and the Q-factor of the complex poles. As the low-frequency resistance remains unchanged, a high dc gain is maintained. Implemented in 0.13 $\mu$ m CMOS process, the proposed design occupies an area of 0.0032 mm 2 and consumes a quiescent current of 10.5 $\mu$ A. When driving a 560 pF Capacitive Load, it achieves a unity-gain frequency of 3.49 MHz, an average slew rate of 0.86 V/ $\mu$ s, and an average settling time of 0.9 $\mu$ s.
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An Integrated 1.8V to 3.3V Regulated Voltage Doubler Using Active Diodes and Dual-Loop Voltage Follower for Switch-Capacitive Load
2006 Symposium on VLSI Circuits 2006. Digest of Technical Papers., 2006Co-Authors: Yat Hei Lam, Wing Hung Ki, Chi-ying TsuiAbstract:An integrated 1.8V to 3.3V regulated voltage doubler is presented. Active diodes realized by MOS transistors only are employed to prevent reverse charge transfer. The switching low dropout regulator consists of a dual-loop voltage follower that could drive a large switch-Capacitive Load and achieves a fast Load transient of less than 5mus for a 140mA current step. The regulated doubler was fabricated in a 0.35mum CMOS process occupying an area of 0.74mm2
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three stage large Capacitive Load amplifier with damping factor control frequency compensation
IEEE Journal of Solid-state Circuits, 2000Co-Authors: Ka Nang Leung, Wing Hung KiAbstract:A novel damping-factor-control frequency compensation (DFCFC) technique is presented in this paper with detailed theoretical analysis, This compensation technique improves frequency response, transient response, and power supply rejection for amplifiers, especially when driving large Capacitive Loads, Moreover, the required compensation capacitors are small and can be easily integrated in commercial CMOS process. Amplifiers using DFCPC and nested Miller compensation (NMC) driving two Capacitive Loads, 100 and 1000 pF, were fabricated using a 0.8-/spl mu/m CMOS process with V/sub tn/=0.72 V and V/sub tp/=-0.75 V. For the DFCFC amplifier driving a 1000-pF Load, a 1-MHz gain-bandwidth product, 51/spl deg/ phase margin, 0.33-V//spl mu/s slew rate, 3.54-/spl mu/s settling time, and 426-/spl mu/W power consumption are obtained with integrated compensation capacitors. Compared to the NMC amplifier, the frequency and transient responses of the DFCFC amplifier are improved by one order of magnitude with insignificant increase of the power consumption.
Sung-wan Hong - One of the best experts on this subject based on the ideXlab platform.
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a pseudo single stage amplifier with an adaptively varied medium impedance node for ultra high slew rate and wide range Capacitive Load drivability
IEEE Transactions on Circuits and Systems, 2016Co-Authors: Sung-wan HongAbstract:This paper presents a pseudo single-stage (PSS) amplifier with an adaptively varied medium impedance node to achieve an ultra-high slew rate (SR) and at the same time stable operation in a wide Capacitive Load range. Owing to the characteristics of the proposed technique, this amplifier achieves a 1.1-to-8.67 $\text{V}/\mu\text{s}$ slew rate and a 0.01-to-1.66 MHz unity gain frequency over a 0.1-to-15 nF Capacitive Load $(C_{L})$ with an over 69° phase margin while consuming a total quiescent power of only 7.4 $\mu\text{W}$ . This chip was fabricated in a 0.18 $\mu\text{m}$ CMOS process with a silicon area of 0.0021 mm2.
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7 4μw ultra high slew rate pseudo single stage amplifier driving 0 1 to 15nf Capacitive Load with 69 phase margin
Symposium on VLSI Circuits, 2015Co-Authors: Sung-wan Hong, Gyu-hyeong ChoAbstract:To achieve ultra-high slew-rate with stable operation under wide Capacitive Load range, pseudo single-stage amplifier is proposed in this paper. The proposed amplifier achieves widest Capacitive Load drivability (x150). Also, this work achieves at least 151 times larger FOM for slew-rate compared to state-of-the-art works. This chip was fabricated using a 0.18 μm CMOS process with area of 0.0021 mm2.
J B Kuo - One of the best experts on this subject based on the ideXlab platform.
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a 1 5 v full swing bootstrapped cmos large Capacitive Load driver circuit suitable for low voltage cmos vlsi
IEEE Journal of Solid-state Circuits, 1997Co-Authors: J H Lou, J B KuoAbstract:This paper reports a 1.5-V full-swing bootstrapped CMOS large Capacitive-Load driver circuit using two bootstrap capacitors to enhance the switching speed for low-voltage CMOS VLSI. For a supply voltage of 1.5 V, the full-swing bootstrapped CMOS driver circuit shows a 2.2 times improvement in switching speed in driving a Capacitive Load of 10 pF as compared to the conventional CMOS driver circuit. Even for a supply voltage of 1 V, this full-swing bootstrapped CMOS large Capacitive-Load driver circuit is still advantageous.
Gyu-hyeong Cho - One of the best experts on this subject based on the ideXlab platform.
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7 4μw ultra high slew rate pseudo single stage amplifier driving 0 1 to 15nf Capacitive Load with 69 phase margin
Symposium on VLSI Circuits, 2015Co-Authors: Sung-wan Hong, Gyu-hyeong ChoAbstract:To achieve ultra-high slew-rate with stable operation under wide Capacitive Load range, pseudo single-stage amplifier is proposed in this paper. The proposed amplifier achieves widest Capacitive Load drivability (x150). Also, this work achieves at least 151 times larger FOM for slew-rate compared to state-of-the-art works. This chip was fabricated using a 0.18 μm CMOS process with area of 0.0021 mm2.
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17 3 a 0 9v 6 3μw multistage amplifier driving 500pf Capacitive Load with 1 34mhz gbw
International Solid-State Circuits Conference, 2014Co-Authors: Hyun-sik Kim, Gyu-hyeong ChoAbstract:As process scales down, low-voltage, low-power, multistage amplifiers capable of driving a large Capacitive Load with wide bandwidth are becoming more important for various applications. The conventional frequency compensation methods, however, are based on cumbersome transfer function derivations or complicated local loop analysis, inhibiting intuitive understanding. An approach is presented in this paper, which generates insight for the poles and zeros through distinctive compensation analysis, and is applicable to large-number-stage amplifiers. The approach applies feedback theory and simplifies high-frequency Miller amplifiers, thereby reducing orders of circuits and improving insight.