The Experts below are selected from a list of 4548 Experts worldwide ranked by ideXlab platform
Tien-sheng Chao - One of the best experts on this subject based on the ideXlab platform.
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Junctionless Poly-Si Nanowire Transistors With Low-Temperature Trimming Process for Monolithic 3-D IC Application
IEEE Transactions on Electron Devices, 2016Co-Authors: Chun-chieh Chin, Tien-sheng ChaoAbstract:In this paper, the junctionless (JL) ultrathin polycrystalline-Si (poly-Si) nanowire (NW) transistors with gate-all-around configuration and raised source/drain were successfully fabricated by a low-temperature trimming process. The 140 °C-heated phosphoric acid (HPA) was adopted for trimming the Channel Dimension, which exhibits a near roughness degradation-free etching and excellent trimming uniformity. As the HPA immersing time increased, the Channel Dimension was thinned and narrowed, resulting in the greater electrostatic integrity. Therefore, the steep subthreshold swing ~75 mV/decade, low drain-induced barrier lowering ~33 mV/V, and high on/off currents ratio ( $I_{\mathrm{\scriptscriptstyle ON}}/I_{\mathrm{\scriptscriptstyle OFF}}) \sim 7 \times 10^{6}$ can be achieved. These superior characteristics of low-temperature JL poly-Si NW transistors are promising candidates for the low thermal budget monolithic 3-D ICs and the system on panel applications in the future.
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Junctionless Poly-Si Nanowire Transistors With Low-Temperature Trimming Process for Monolithic 3-D IC Application
IEEE Transactions on Electron Devices, 2016Co-Authors: Chun-chieh Chin, Tien-sheng ChaoAbstract:In this paper, the junctionless (JL) ultrathin polycrystalline-Si (poly-Si) nanowire (NW) transistors with gate-all-around configuration and raised source/drain were successfully fabricated by a low-temperature trimming process. The 140 °C-heated phosphoric acid (HPA) was adopted for trimming the Channel Dimension, which exhibits a near roughness degradation-free etching and excellent trimming uniformity. As the HPA immersing time increased, the Channel Dimension was thinned and narrowed, resulting in the greater electrostatic integrity. Therefore, the steep subthreshold swing ~75 mV/decade, low drain-induced barrier lowering ~33 mV/V, and high on/off currents ratio (ION/IOFF) ~ 7 x 106 can be achieved. These superior characteristics of low-temperature JL poly-Si NW transistors are promising candidates for the low thermal budget monolithic 3-D ICs and the system on panel applications in the future.
Chun-chieh Chin - One of the best experts on this subject based on the ideXlab platform.
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Junctionless Poly-Si Nanowire Transistors With Low-Temperature Trimming Process for Monolithic 3-D IC Application
IEEE Transactions on Electron Devices, 2016Co-Authors: Chun-chieh Chin, Tien-sheng ChaoAbstract:In this paper, the junctionless (JL) ultrathin polycrystalline-Si (poly-Si) nanowire (NW) transistors with gate-all-around configuration and raised source/drain were successfully fabricated by a low-temperature trimming process. The 140 °C-heated phosphoric acid (HPA) was adopted for trimming the Channel Dimension, which exhibits a near roughness degradation-free etching and excellent trimming uniformity. As the HPA immersing time increased, the Channel Dimension was thinned and narrowed, resulting in the greater electrostatic integrity. Therefore, the steep subthreshold swing ~75 mV/decade, low drain-induced barrier lowering ~33 mV/V, and high on/off currents ratio ( $I_{\mathrm{\scriptscriptstyle ON}}/I_{\mathrm{\scriptscriptstyle OFF}}) \sim 7 \times 10^{6}$ can be achieved. These superior characteristics of low-temperature JL poly-Si NW transistors are promising candidates for the low thermal budget monolithic 3-D ICs and the system on panel applications in the future.
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Junctionless Poly-Si Nanowire Transistors With Low-Temperature Trimming Process for Monolithic 3-D IC Application
IEEE Transactions on Electron Devices, 2016Co-Authors: Chun-chieh Chin, Tien-sheng ChaoAbstract:In this paper, the junctionless (JL) ultrathin polycrystalline-Si (poly-Si) nanowire (NW) transistors with gate-all-around configuration and raised source/drain were successfully fabricated by a low-temperature trimming process. The 140 °C-heated phosphoric acid (HPA) was adopted for trimming the Channel Dimension, which exhibits a near roughness degradation-free etching and excellent trimming uniformity. As the HPA immersing time increased, the Channel Dimension was thinned and narrowed, resulting in the greater electrostatic integrity. Therefore, the steep subthreshold swing ~75 mV/decade, low drain-induced barrier lowering ~33 mV/V, and high on/off currents ratio (ION/IOFF) ~ 7 x 106 can be achieved. These superior characteristics of low-temperature JL poly-Si NW transistors are promising candidates for the low thermal budget monolithic 3-D ICs and the system on panel applications in the future.
Cheng-ting Shih - One of the best experts on this subject based on the ideXlab platform.
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threshold voltage and transconductance shifting reliance on strained sige Channel Dimension
Solid-state Electronics, 2015Co-Authors: Wen-teng Chang, Cheng-ting ShihAbstract:Abstract Compared with a control Si p-Channel, a compressive SiGe p-Channel degrades as the width-to-length ( W / L ) ratio increases beyond a critical value. This ratio varies at different areas of a wafer. The threshold voltage and transconductance differences between a strained SiGe and a control Si p-Channel augment as the W / L ratio increases. However, the transconductance difference in an n-Channel diminishes as the ratio increases, which can be explained by the prominent longitudinal or transverse configuration of the piezoresistance coefficients of [1 1 0] SiGe. The interfacial stress between a capsulated Si and SiGe can be approximated by comparing the degradations of a strained SiGe and that of a control Si Channel.
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Threshold voltage and transconductance shifting reliance on strained-SiGe Channel Dimension
2014 7th International Silicon-Germanium Technology and Device Meeting (ISTDM), 2014Co-Authors: Wen-teng Chang, Cheng-ting ShihAbstract:Both threshold voltage and transconductance shifting of cap Si and SiGe are consistent with the tendency of the W/L ratio. However, the variation of this critical ratio for the enhancement or degradation in p-Channel at different cut areas implies the importance of process stability. The piezoresistance coefficients of [110] strained SiGe elucidates the enhancement or degradation of both p-/n-Channels.
H. Y. Yu - One of the best experts on this subject based on the ideXlab platform.
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Junction-less stackable SONOS memory realized on vertical-Si-nanowire for 3-D application
Proceedings of 2011 International Symposium on VLSI Technology Systems and Applications, 2011Co-Authors: H. Y. Yu, N. Singh, T. T. Le, E. Gnani, G. Baccarani, K. C. Leong, G. Q. Lo, D. L. KwongAbstract:This work demonstrates a new type of SONOS memory in which there are no junctions. These junction-less (JL) devices are realized on vertical Si nanowire gate all-around structure with Channel Dimension down to 20nm and have comparable electrical characteristics (SS
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Junction-less stackable SONOS memory realized on vertical-Si-nanowire for 3-D application
Proceedings of 2011 International Symposium on VLSI Technology Systems and Applications, 2011Co-Authors: H. Y. Yu, N. Singh, T. T. Le, E. Gnani, G. Baccarani, K. C. Leong, G. Q. Lo, D. L. KwongAbstract:This work demonstrates a new type of SONOS memory in which there are no junctions. These junction-less (JL) devices are realized on vertical Si nanowire gate all-around structure with Channel Dimension down to 20nm and have comparable electrical characteristics (SS < 70mV/dec, leakage current
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Demonstration of memory string with stacked junction-less SONOS realized on vertical silicon nanowire
2011 International Electron Devices Meeting, 2011Co-Authors: H. Y. Yu, N. Singh, K. C. Leong, E. Quek, G.q. Lo, D. L. KwongAbstract:We demonstrated a NAND memory string based on 2-level stacked junction-less (JL) gate-all-around (GAA) SONOS cells fabricated on vertical Si nanowire (SiNW) platform with footprint of 6F2/2. The stacked SiNW memory cells with Channel Dimension down to 30 nm exhibit well-behaved memory characteristics such as program/erase (P/E) speeds, endurance, retention and program disturb properties. The vertically stacked device structure improves the bit density and the absence of junctions reduces the process complexity/cost and makes this device manufacturable with very low thermal budget.
D. L. Kwong - One of the best experts on this subject based on the ideXlab platform.
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Junction-less stackable SONOS memory realized on vertical-Si-nanowire for 3-D application
Proceedings of 2011 International Symposium on VLSI Technology Systems and Applications, 2011Co-Authors: H. Y. Yu, N. Singh, T. T. Le, E. Gnani, G. Baccarani, K. C. Leong, G. Q. Lo, D. L. KwongAbstract:This work demonstrates a new type of SONOS memory in which there are no junctions. These junction-less (JL) devices are realized on vertical Si nanowire gate all-around structure with Channel Dimension down to 20nm and have comparable electrical characteristics (SS
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Junction-less stackable SONOS memory realized on vertical-Si-nanowire for 3-D application
Proceedings of 2011 International Symposium on VLSI Technology Systems and Applications, 2011Co-Authors: H. Y. Yu, N. Singh, T. T. Le, E. Gnani, G. Baccarani, K. C. Leong, G. Q. Lo, D. L. KwongAbstract:This work demonstrates a new type of SONOS memory in which there are no junctions. These junction-less (JL) devices are realized on vertical Si nanowire gate all-around structure with Channel Dimension down to 20nm and have comparable electrical characteristics (SS < 70mV/dec, leakage current