The Experts below are selected from a list of 327 Experts worldwide ranked by ideXlab platform

Maryam Shojaei Baghini - One of the best experts on this subject based on the ideXlab platform.

  • design of a novel highly emi immune cmos miller opamp considering Channel Length Modulation
    IEEE Transactions on Circuits and Systems I-regular Papers, 2017
    Co-Authors: Subrahmanyam Boyapati, Jean-michel Redouté, Maryam Shojaei Baghini
    Abstract:

    This paper presents a novel CMOS Miller operational amplifier (OpAmp) that has high immunity to electromagnetic interference (EMI). The proposed CMOS Miller OpAmp uses the replica concept with the source-buffered technique in order to achieve high EMI immunity across a wide range of frequencies (10 MHz to 1 GHz). The proposed amplifier is designed using the first-order quadratic mathematical model. The modeling includes the body effect and Channel Length Modulation. The circuit has been fabricated using 0.18 $\mu \text{m}$ mixed-mode CMOS technology. Measurement results illustrate how the proposed Miller OpAmp reduces susceptibility to EMI even in the presence of high-amplitude interferences that are as high as 1 Vpp. Experimental results show that the maximum EMI-induced output offset voltage for the proposed Miller OpAmp is less than 10 mV over a wide range of frequencies (10 MHz to 1 GHz) when a 900 mVpp EMI signal is injected into the noninverting input. In contrast, the classic Miller OpAmp generates a maximum output offset voltage of 215 mV at 1 GHz under the same operating conditions. The measured results of the EMI-induced input offset corroborates the circuit simulations.

  • Design of A Novel Highly EMI-Immune CMOS Miller OpAmp Considering Channel Length Modulation
    IEEE Transactions on Circuits and Systems I: Regular Papers, 2017
    Co-Authors: Subrahmanyam Boyapati, Jean-michel Redouté, Maryam Shojaei Baghini
    Abstract:

    This paper presents a novel CMOS Miller operational amplifier (OpAmp) that has high immunity to electromagnetic interference (EMI). The proposed CMOS Miller OpAmp uses the replica concept with the source-buffered technique in order to achieve high EMI immunity across a wide range of frequencies (10 MHz to 1 GHz). The proposed amplifier is designed using the first-order quadratic mathematical model. The modeling includes the body effect and Channel Length Modulation. The circuit has been fabricated using 0.18 μm mixed-mode CMOS technology. Measurement results illustrate how the proposed Miller OpAmp reduces susceptibility to EMI even in the presence of high-amplitude interferences that are as high as 1 Vpp. Experimental results show that the maximum EMI-induced output offset voltage for the proposed Miller OpAmp is less than 10 mV over a wide range of frequencies (10 MHz to 1 GHz) when a 900 mVpp EMI signal is injected into the noninverting input. In contrast, the classic Miller OpAmp generates a maximum output offset voltage of 215 mV at 1 GHz under the same operating conditions. The measured results of the EMI-induced input offset corroborates the circuit simulations.

Subrahmanyam Boyapati - One of the best experts on this subject based on the ideXlab platform.

  • design of a novel highly emi immune cmos miller opamp considering Channel Length Modulation
    IEEE Transactions on Circuits and Systems I-regular Papers, 2017
    Co-Authors: Subrahmanyam Boyapati, Jean-michel Redouté, Maryam Shojaei Baghini
    Abstract:

    This paper presents a novel CMOS Miller operational amplifier (OpAmp) that has high immunity to electromagnetic interference (EMI). The proposed CMOS Miller OpAmp uses the replica concept with the source-buffered technique in order to achieve high EMI immunity across a wide range of frequencies (10 MHz to 1 GHz). The proposed amplifier is designed using the first-order quadratic mathematical model. The modeling includes the body effect and Channel Length Modulation. The circuit has been fabricated using 0.18 $\mu \text{m}$ mixed-mode CMOS technology. Measurement results illustrate how the proposed Miller OpAmp reduces susceptibility to EMI even in the presence of high-amplitude interferences that are as high as 1 Vpp. Experimental results show that the maximum EMI-induced output offset voltage for the proposed Miller OpAmp is less than 10 mV over a wide range of frequencies (10 MHz to 1 GHz) when a 900 mVpp EMI signal is injected into the noninverting input. In contrast, the classic Miller OpAmp generates a maximum output offset voltage of 215 mV at 1 GHz under the same operating conditions. The measured results of the EMI-induced input offset corroborates the circuit simulations.

  • Design of A Novel Highly EMI-Immune CMOS Miller OpAmp Considering Channel Length Modulation
    IEEE Transactions on Circuits and Systems I: Regular Papers, 2017
    Co-Authors: Subrahmanyam Boyapati, Jean-michel Redouté, Maryam Shojaei Baghini
    Abstract:

    This paper presents a novel CMOS Miller operational amplifier (OpAmp) that has high immunity to electromagnetic interference (EMI). The proposed CMOS Miller OpAmp uses the replica concept with the source-buffered technique in order to achieve high EMI immunity across a wide range of frequencies (10 MHz to 1 GHz). The proposed amplifier is designed using the first-order quadratic mathematical model. The modeling includes the body effect and Channel Length Modulation. The circuit has been fabricated using 0.18 μm mixed-mode CMOS technology. Measurement results illustrate how the proposed Miller OpAmp reduces susceptibility to EMI even in the presence of high-amplitude interferences that are as high as 1 Vpp. Experimental results show that the maximum EMI-induced output offset voltage for the proposed Miller OpAmp is less than 10 mV over a wide range of frequencies (10 MHz to 1 GHz) when a 900 mVpp EMI signal is injected into the noninverting input. In contrast, the classic Miller OpAmp generates a maximum output offset voltage of 215 mV at 1 GHz under the same operating conditions. The measured results of the EMI-induced input offset corroborates the circuit simulations.

Jean-michel Redouté - One of the best experts on this subject based on the ideXlab platform.

  • design of a novel highly emi immune cmos miller opamp considering Channel Length Modulation
    IEEE Transactions on Circuits and Systems I-regular Papers, 2017
    Co-Authors: Subrahmanyam Boyapati, Jean-michel Redouté, Maryam Shojaei Baghini
    Abstract:

    This paper presents a novel CMOS Miller operational amplifier (OpAmp) that has high immunity to electromagnetic interference (EMI). The proposed CMOS Miller OpAmp uses the replica concept with the source-buffered technique in order to achieve high EMI immunity across a wide range of frequencies (10 MHz to 1 GHz). The proposed amplifier is designed using the first-order quadratic mathematical model. The modeling includes the body effect and Channel Length Modulation. The circuit has been fabricated using 0.18 $\mu \text{m}$ mixed-mode CMOS technology. Measurement results illustrate how the proposed Miller OpAmp reduces susceptibility to EMI even in the presence of high-amplitude interferences that are as high as 1 Vpp. Experimental results show that the maximum EMI-induced output offset voltage for the proposed Miller OpAmp is less than 10 mV over a wide range of frequencies (10 MHz to 1 GHz) when a 900 mVpp EMI signal is injected into the noninverting input. In contrast, the classic Miller OpAmp generates a maximum output offset voltage of 215 mV at 1 GHz under the same operating conditions. The measured results of the EMI-induced input offset corroborates the circuit simulations.

  • Design of A Novel Highly EMI-Immune CMOS Miller OpAmp Considering Channel Length Modulation
    IEEE Transactions on Circuits and Systems I: Regular Papers, 2017
    Co-Authors: Subrahmanyam Boyapati, Jean-michel Redouté, Maryam Shojaei Baghini
    Abstract:

    This paper presents a novel CMOS Miller operational amplifier (OpAmp) that has high immunity to electromagnetic interference (EMI). The proposed CMOS Miller OpAmp uses the replica concept with the source-buffered technique in order to achieve high EMI immunity across a wide range of frequencies (10 MHz to 1 GHz). The proposed amplifier is designed using the first-order quadratic mathematical model. The modeling includes the body effect and Channel Length Modulation. The circuit has been fabricated using 0.18 μm mixed-mode CMOS technology. Measurement results illustrate how the proposed Miller OpAmp reduces susceptibility to EMI even in the presence of high-amplitude interferences that are as high as 1 Vpp. Experimental results show that the maximum EMI-induced output offset voltage for the proposed Miller OpAmp is less than 10 mV over a wide range of frequencies (10 MHz to 1 GHz) when a 900 mVpp EMI signal is injected into the noninverting input. In contrast, the classic Miller OpAmp generates a maximum output offset voltage of 215 mV at 1 GHz under the same operating conditions. The measured results of the EMI-induced input offset corroborates the circuit simulations.

Gaspard Hiblot - One of the best experts on this subject based on the ideXlab platform.

  • dibl compensated extraction of the Channel Length Modulation coefficient in mosfets
    IEEE Transactions on Electron Devices, 2018
    Co-Authors: Gaspard Hiblot
    Abstract:

    In this brief, a new Channel Length Modulation (CLM) extraction method is proposed. The main innovation of this approach is that the extracted value of CLM is not artificially inflated by the contribution of the drain-induced barrier lowering (DIBL), which allows discriminating between the two phenomena. In this method, the transistor gain is measured by using the source-measurement unit in a forced current mode. It is demonstrated that the CLM coefficient can be extracted by the linear regression of the inverse of the gain with respect to the current-over-transconductance ratio, corrected for series resistances. This method is later applied and validated on a planar bulk 65-nm CMOS technology.

  • DIBL–Compensated Extraction of the Channel Length Modulation Coefficient in MOSFETs
    IEEE Transactions on Electron Devices, 2018
    Co-Authors: Gaspard Hiblot
    Abstract:

    In this brief, a new Channel Length Modulation (CLM) extraction method is proposed. The main innovation of this approach is that the extracted value of CLM is not artificially inflated by the contribution of the drain-induced barrier lowering (DIBL), which allows discriminating between the two phenomena. In this method, the transistor gain is measured by using the source-measurement unit in a forced current mode. It is demonstrated that the CLM coefficient can be extracted by the linear regression of the inverse of the gain with respect to the current-over-transconductance ratio, corrected for series resistances. This method is later applied and validated on a planar bulk 65-nm CMOS technology.

Michael S. Shur - One of the best experts on this subject based on the ideXlab platform.

  • Ion-implanted 0.4 /spl mu/m wide 2-D MESFET for low power electronics
    Electronics Letters, 1996
    Co-Authors: M. Hurt, Michael S. Shur, W.c.b. Peatman, R. Tsai, Trond Ytterdal, B J Moon
    Abstract:

    Two-dimensional (2-D) MESFETs with 0.4 /spl mu/m Channel widths have been fabricated on ion-implanted n-GaAs material. The 2-D MESFET uses sidewall Schottky contacts on either side of an Si-doped Channel to laterally modulate the current. The peak drain current is 370 mA/mm and the peak transconductance is 295 mS/mm at room temperature. The narrow Channel effect and Channel Length Modulation have been reduced in this device.

  • new short Channel n mosfet current voltage model in strong inversion and unified parameter extraction method
    IEEE Transactions on Electron Devices, 1991
    Co-Authors: B J Moon, C K Park, Michael S. Shur
    Abstract:

    A semiempirical strong inversion current-voltage (I-V) model for submicrometer n-Channel MOSFETs which is suitable for circuit simulation and rapid process characterization is proposed. The model is based on a more accurate velocity-field relationship in the linear region and finite drain conductance due to the Channel Length Modulation effect in the saturation region. The parameter extraction starts from the experimental determination of the MOSFET saturation current and saturation voltage by differentiating the output characteristics in a unified and unambiguous way. These results are used in order to systematically extract the device and process parameters such as the effective electron saturation velocity and mobility, drain and source series resistances, effective gate Length and characteristic Length for Channel Length Modulation, and short-Channel effects. The values agree well with other independent measurements. The results of experimental studies of wide n-MOSFETs with nominal gate Length of 0.8, 1.0, and 1.2 mu m fabricated by an n-well CMOS process are reported. The calculated I-V characteristics using the extracted parameters show excellent agreement with the measurement results. >

  • New Short-Channel n-MOSFET Current-Voltage Model in Strong Inversion and Unified Parameter Extraction Method Byung-Jong Moon, Student Member, IEEE, Chan-Kwang Park, Student Member, IEEE,
    1991
    Co-Authors: Michael S. Shur
    Abstract:

    We propose a new semi-empirical strong inversion cur- rent-voltage (I-V) model for submicrometer n-Channel MOSFET's which is suitable for circuit simulation and rapid process character- ization. Our model is based on a more accurate velocity-field relation- ship in the linear region and finite drain conductance due to Channel Length Modulation effect in the saturation region. Our parameter ex- traction starts from the experimental determination of the MOSFET saturation current and saturation voltage by differentiating the output characteristics in a unified and unambiguous way. We use these results in order to extract the device and process parameters such as the effective electron saturation velocity and mobility, drain and source series resistances, effective gate Length and characteristic Length for Channel Length Modulation, and short-Channel effects systematically. The deduced values agree well with other independent measurements. We report the results of experimental studies of wide n-MOSFET's with nominal gate Lengths of 0.8, 1.0, and 1.2 pm fabricated by n-well CMOS process. The calculated I-V characteristics using the extracted parameters show excellent agreement with the measurement results. The salient feature of our approach is that it allows the automatic pa- rameter extraction in a systematic and unified manner, which is ex- tremely versatile for statistical yield analysis due to parameter varia- tion.