The Experts below are selected from a list of 303 Experts worldwide ranked by ideXlab platform

S Mutoh - One of the best experts on this subject based on the ideXlab platform.

  • 1 v power supply high speed digital Circuit Technology with multithreshold voltage cmos
    IEEE Journal of Solid-state Circuits, 1995
    Co-Authors: S Mutoh, Takakuni Douseki, Y Matsuya, Takao Aoki, Satoshi Shigematsu, Junzo Yamada
    Abstract:

    1-V power supply high-speed low-power digital Circuit Technology with 0.5-/spl mu/m multithreshold-voltage CMOS (MTCMOS) is proposed. This Technology features both low-threshold voltage and high-threshold voltage MOSFET's in a single LSI. The low-threshold voltage MOSFET's enhance speed performance at a low supply voltage of 1 V or less, while the high-threshold voltage MOSFET's suppress the stand-by leakage current during the sleep period. This Technology has brought about logic gate characteristics of a 1.7-ns propagation delay time and 0.3-/spl mu/W/MHz/gate power dissipation with a standard load. In addition, an MTCMOS standard cell library has been developed so that conventional CAD tools can be used to lay out low-voltage LSI's. To demonstrate MTCMOS's effectiveness, a PLL LSI based on standard cells was designed as a carrying vehicle. 18-MHz operation at 1 V was achieved using a 0.5-/spl mu/m CMOS process. >

  • 1v high speed digital Circuit Technology with 0 5 spl mu m multi threshold cmos
    International Conference on ASIC, 1993
    Co-Authors: S Mutoh, T Douseki, Y Matsuya, Takao Aoki, J. Yamada
    Abstract:

    A 1-V high-speed and low-power digital Circuit Technology with 0.5/spl mu/m multi-threshold CMOS (MT-CMOS) is proposed. This Technology applies both low-threshold voltage and high-threshold voltage MOSFETs in one LSI. Low-threshold voltage MOSFETs enhance speed performance at a supply voltage of 1 V or less. High-threshold voltage MOSFETs suppress the stand-by leakage Circuit during the sleep period. The Technology has achieved logic gate characteristics of a 1.7-ns propagation delay time and 0.3-/spl mu/W/MHz/gate power dissipation. To demonstrate its effectiveness, a standard cell based PLL-LSI was designed as a carrying vehicle. An 18-MHz operation at 1 V was obtained using a 0.5-/spl mu/m MT-CMOS process. >

Takakuni Douseki - One of the best experts on this subject based on the ideXlab platform.

  • Ultralow-power CMOS/SOI Circuit Technology
    Electrical Engineering in Japan, 2008
    Co-Authors: Yuichi Kado, Takakuni Douseki, Yasuyuki Matsuya, Tsuneo Tsukahara
    Abstract:

    We have introduced an example of a system that embodies the concept of a ubiquitous communication service and explained the importance of low power consumption in the communicator that will serve as the bridge between the real world and the network for real-time services in which sensor data is acquired every second. An effective solution to the problem of high energy efficiency is to employ the synergy of combining low-voltage analog Circuit Technology and FD-SOI devices. Taking advantage of that synergy to reduce the power consumption of the communicator during operation to about 10 mW and employing intermittent operation with an activity rate of less than l% would make it possible to support operation for 1 year or more with a commercial coin-type lithium battery. © 2007 Wiley Periodicals, Inc. Electr Eng Jpn, 162(3): 38–43, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/eej.20543

  • Ultralow-power CMOS/SOI Circuit Technology
    Ieej Transactions on Electronics Information and Systems, 2006
    Co-Authors: Yuichi Kado, Takakuni Douseki, Yasuyuki Matsuya, Tsuneo Tsukahara
    Abstract:

    We have introduced an example of a system that embodies the concept of a ubiquitous communication service and explained the importance of low power consumption in the communicator that will serve as the bridge between the real world and the network for real-time services in which sensor data is acquired every second. An effective solution to the problem of high energy efficiency is to employ the synergy of combining low-voltage analog Circuit Technology and FD-SOI devices. Taking advantage of that synergy to reduce the power consumption of the communicator during operation to about 10 mW and employing intermittent operation with an activity rate of less than 1% would make it possible to support operation for one year or more with a commercial coin-type lithium battery.

  • A batteryless wireless system with MTCMOS/SOI Circuit Technology
    Proceedings of the IEEE 2003 Custom Integrated Circuits Conference 2003., 2003
    Co-Authors: Takakuni Douseki, Tsuneo Tsukahara, Y. Yoshida, F. Utsunomiya, N. Hama
    Abstract:

    Ultralow-power multi-threshold (MT) CMOS/SOI Circuit Technology, which makes it possible to lower the supply voltage of the LSIs to 0.5 V and reduce the power dissipation of 1-mW level, provides self-powered batteryless operation for short-range wireless systems. We overview MTCMOS/SOI Circuit Technology and describe some batteryless wireless systems built using MTCMOS/SOI LSIs.

  • SOI Circuit Technology for batteryless mobile system with green energy sources
    2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302), 2002
    Co-Authors: N. Hama, Tsuneo Tsukahara, Y. Yoshida, F. Utsunomiya, A. Yajima, Junichi Kodate, Takakuni Douseki
    Abstract:

    Energy-extracted Circuit Technology for green energy sources and ultralow-power SOI Circuit Technology with 1 mW level power dissipation provide self-powered operation of mobile equipment. A variable-stage switched-capacitor-type DC-DC converter scheme makes it possible to supply a constant voltage to LSIs for green energy sources. A 1-V 300 MHz-band voltage-controlled SAW oscillator Circuit and a 0.5-V CPU fabricated with 0.35-/spl mu/m FD-SOI process are described. We verify the effectiveness of these Circuits at self-powered wireless mobile system.

  • 1 v power supply high speed digital Circuit Technology with multithreshold voltage cmos
    IEEE Journal of Solid-state Circuits, 1995
    Co-Authors: S Mutoh, Takakuni Douseki, Y Matsuya, Takao Aoki, Satoshi Shigematsu, Junzo Yamada
    Abstract:

    1-V power supply high-speed low-power digital Circuit Technology with 0.5-/spl mu/m multithreshold-voltage CMOS (MTCMOS) is proposed. This Technology features both low-threshold voltage and high-threshold voltage MOSFET's in a single LSI. The low-threshold voltage MOSFET's enhance speed performance at a low supply voltage of 1 V or less, while the high-threshold voltage MOSFET's suppress the stand-by leakage current during the sleep period. This Technology has brought about logic gate characteristics of a 1.7-ns propagation delay time and 0.3-/spl mu/W/MHz/gate power dissipation with a standard load. In addition, an MTCMOS standard cell library has been developed so that conventional CAD tools can be used to lay out low-voltage LSI's. To demonstrate MTCMOS's effectiveness, a PLL LSI based on standard cells was designed as a carrying vehicle. 18-MHz operation at 1 V was achieved using a 0.5-/spl mu/m CMOS process. >

Junzo Yamada - One of the best experts on this subject based on the ideXlab platform.

  • 1 v power supply high speed digital Circuit Technology with multithreshold voltage cmos
    IEEE Journal of Solid-state Circuits, 1995
    Co-Authors: S Mutoh, Takakuni Douseki, Y Matsuya, Takao Aoki, Satoshi Shigematsu, Junzo Yamada
    Abstract:

    1-V power supply high-speed low-power digital Circuit Technology with 0.5-/spl mu/m multithreshold-voltage CMOS (MTCMOS) is proposed. This Technology features both low-threshold voltage and high-threshold voltage MOSFET's in a single LSI. The low-threshold voltage MOSFET's enhance speed performance at a low supply voltage of 1 V or less, while the high-threshold voltage MOSFET's suppress the stand-by leakage current during the sleep period. This Technology has brought about logic gate characteristics of a 1.7-ns propagation delay time and 0.3-/spl mu/W/MHz/gate power dissipation with a standard load. In addition, an MTCMOS standard cell library has been developed so that conventional CAD tools can be used to lay out low-voltage LSI's. To demonstrate MTCMOS's effectiveness, a PLL LSI based on standard cells was designed as a carrying vehicle. 18-MHz operation at 1 V was achieved using a 0.5-/spl mu/m CMOS process. >

Tsuneo Tsukahara - One of the best experts on this subject based on the ideXlab platform.

  • Ultralow-power CMOS/SOI Circuit Technology
    Electrical Engineering in Japan, 2008
    Co-Authors: Yuichi Kado, Takakuni Douseki, Yasuyuki Matsuya, Tsuneo Tsukahara
    Abstract:

    We have introduced an example of a system that embodies the concept of a ubiquitous communication service and explained the importance of low power consumption in the communicator that will serve as the bridge between the real world and the network for real-time services in which sensor data is acquired every second. An effective solution to the problem of high energy efficiency is to employ the synergy of combining low-voltage analog Circuit Technology and FD-SOI devices. Taking advantage of that synergy to reduce the power consumption of the communicator during operation to about 10 mW and employing intermittent operation with an activity rate of less than l% would make it possible to support operation for 1 year or more with a commercial coin-type lithium battery. © 2007 Wiley Periodicals, Inc. Electr Eng Jpn, 162(3): 38–43, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/eej.20543

  • Ultralow-power CMOS/SOI Circuit Technology
    Ieej Transactions on Electronics Information and Systems, 2006
    Co-Authors: Yuichi Kado, Takakuni Douseki, Yasuyuki Matsuya, Tsuneo Tsukahara
    Abstract:

    We have introduced an example of a system that embodies the concept of a ubiquitous communication service and explained the importance of low power consumption in the communicator that will serve as the bridge between the real world and the network for real-time services in which sensor data is acquired every second. An effective solution to the problem of high energy efficiency is to employ the synergy of combining low-voltage analog Circuit Technology and FD-SOI devices. Taking advantage of that synergy to reduce the power consumption of the communicator during operation to about 10 mW and employing intermittent operation with an activity rate of less than 1% would make it possible to support operation for one year or more with a commercial coin-type lithium battery.

  • A batteryless wireless system with MTCMOS/SOI Circuit Technology
    Proceedings of the IEEE 2003 Custom Integrated Circuits Conference 2003., 2003
    Co-Authors: Takakuni Douseki, Tsuneo Tsukahara, Y. Yoshida, F. Utsunomiya, N. Hama
    Abstract:

    Ultralow-power multi-threshold (MT) CMOS/SOI Circuit Technology, which makes it possible to lower the supply voltage of the LSIs to 0.5 V and reduce the power dissipation of 1-mW level, provides self-powered batteryless operation for short-range wireless systems. We overview MTCMOS/SOI Circuit Technology and describe some batteryless wireless systems built using MTCMOS/SOI LSIs.

  • SOI Circuit Technology for batteryless mobile system with green energy sources
    2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302), 2002
    Co-Authors: N. Hama, Tsuneo Tsukahara, Y. Yoshida, F. Utsunomiya, A. Yajima, Junichi Kodate, Takakuni Douseki
    Abstract:

    Energy-extracted Circuit Technology for green energy sources and ultralow-power SOI Circuit Technology with 1 mW level power dissipation provide self-powered operation of mobile equipment. A variable-stage switched-capacitor-type DC-DC converter scheme makes it possible to supply a constant voltage to LSIs for green energy sources. A 1-V 300 MHz-band voltage-controlled SAW oscillator Circuit and a 0.5-V CPU fabricated with 0.35-/spl mu/m FD-SOI process are described. We verify the effectiveness of these Circuits at self-powered wireless mobile system.

  • Low-power Circuit Technology toward ultra-small network appliances
    Ntt Review, 2002
    Co-Authors: Yuichi Kado, Yasuyuki Matsuya, Tsuneo Tsukahara
    Abstract:

    The realization of Ubiquitous Services calls for the development of various kinds of network appliances. These include compact personal digital assistants that can access the network anywhere and anytime, and network sensor arrays that can collect real-world data on a user's physical condition and the surrounding environment and then send that data out onto the network. This article describes NTT's extremely low-power Circuit Technology that plays a key role in achieving ultra-small network appliances.

Y Matsuya - One of the best experts on this subject based on the ideXlab platform.

  • 1 v power supply high speed digital Circuit Technology with multithreshold voltage cmos
    IEEE Journal of Solid-state Circuits, 1995
    Co-Authors: S Mutoh, Takakuni Douseki, Y Matsuya, Takao Aoki, Satoshi Shigematsu, Junzo Yamada
    Abstract:

    1-V power supply high-speed low-power digital Circuit Technology with 0.5-/spl mu/m multithreshold-voltage CMOS (MTCMOS) is proposed. This Technology features both low-threshold voltage and high-threshold voltage MOSFET's in a single LSI. The low-threshold voltage MOSFET's enhance speed performance at a low supply voltage of 1 V or less, while the high-threshold voltage MOSFET's suppress the stand-by leakage current during the sleep period. This Technology has brought about logic gate characteristics of a 1.7-ns propagation delay time and 0.3-/spl mu/W/MHz/gate power dissipation with a standard load. In addition, an MTCMOS standard cell library has been developed so that conventional CAD tools can be used to lay out low-voltage LSI's. To demonstrate MTCMOS's effectiveness, a PLL LSI based on standard cells was designed as a carrying vehicle. 18-MHz operation at 1 V was achieved using a 0.5-/spl mu/m CMOS process. >

  • 1v high speed digital Circuit Technology with 0 5 spl mu m multi threshold cmos
    International Conference on ASIC, 1993
    Co-Authors: S Mutoh, T Douseki, Y Matsuya, Takao Aoki, J. Yamada
    Abstract:

    A 1-V high-speed and low-power digital Circuit Technology with 0.5/spl mu/m multi-threshold CMOS (MT-CMOS) is proposed. This Technology applies both low-threshold voltage and high-threshold voltage MOSFETs in one LSI. Low-threshold voltage MOSFETs enhance speed performance at a supply voltage of 1 V or less. High-threshold voltage MOSFETs suppress the stand-by leakage Circuit during the sleep period. The Technology has achieved logic gate characteristics of a 1.7-ns propagation delay time and 0.3-/spl mu/W/MHz/gate power dissipation. To demonstrate its effectiveness, a standard cell based PLL-LSI was designed as a carrying vehicle. An 18-MHz operation at 1 V was obtained using a 0.5-/spl mu/m MT-CMOS process. >