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Eby G Friedman - One of the best experts on this subject based on the ideXlab platform.
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case study Clock Distribution Networks for three dimensional ics
Three-Dimensional Integrated Circuit Design (Second Edition), 2017Co-Authors: Vasilis F. Pavlidis, Ioannis Savidis, Eby G FriedmanAbstract:A prototype circuit, the second of the three prototype circuits presented in this book, investigating different global three-dimensional (3-D) Clock Distribution Networks, is described in this chapter. A variety of Clock Networks such as H-trees, rings, tree-like Networks, and trunk-based Networks, are explored in terms of Clock skew and power consumption to determine an effective Clock Distribution network for 3-D ICs. The prototype test circuit composed of these Networks is manufactured by the 3-D fabrication process developed at MIT Lincoln Laboratories. The design and modeling process and related experimental results are also included in this chapter. Power and Clock skew tradeoffs among the different topologies are presented.
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timing driven variation aware synthesis of hybrid mesh tree Clock Distribution Networks
Integration, 2013Co-Authors: Ameer M S Abdelhadi, Ran Ginosar, Avinoam Kolodny, Eby G FriedmanAbstract:Clock skew variations adversely affect timing margins, limiting performance, reducing yield, and may also lead to functional faults. Non-tree Clock Distribution Networks, such as meshes and crosslinks, are employed to reduce skew and also to mitigate skew variations. These Networks, however, increase the dissipated power while consuming significant metal resources. Several methods have been proposed to trade off power and wires to reduce skew. In this paper, an efficient algorithm is presented to reduce Clock skew variations while minimizing power dissipation and metal area overhead. With a combination of nonuniform meshes and unbuffered trees (UBT), a variation-tolerant hybrid Clock Distribution network is produced. Clock skew variations are selectively reduced based on circuit timing information generated by static timing analysis (STA). The skew variation reduction procedure is prioritized for critical timing paths, since these paths are more sensitive to skew variations. A framework for skew variation management is proposed. The algorithm has been implemented in a standard 65nm cell library using standard EDA tools, and tested on several benchmark circuits. As compared to other nonuniform mesh construction methods that do not support managed skew tolerance, experimental results exhibit a 41% average reduction in metal area and a 43% average reduction in power dissipation. As compared to other methods that employ skew tolerance management techniques but do not use a hybrid Clock topology, an 8% average reduction in metal area and a 9% average reduction in power dissipation are achieved.
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Clock Distribution Networks in 3 d integrated systems
IEEE Transactions on Very Large Scale Integration Systems, 2011Co-Authors: Vasilis F. Pavlidis, Ioannis Savidis, Eby G FriedmanAbstract:3-D integration is an important technology that addresses fundamental limitations in on-chip interconnects. Several design issues related to 3-D circuits, such as multiplane synchronization, however, need to be addressed. A comparison of three 3-D Clock Distribution network topologies is presented in this paper. Good agreement is shown between the modeled and experimental results of a 3-D test circuit composed of three device planes. Successful operation of the 3-D test circuit at 1.4 GHz is demonstrated. Clock skew, Clock delay, signal slew, and power dissipation measurements for the different Clock topologies are also provided. The measurements suggest that each topology provides certain advantages and disadvantages in terms of different performance criteria. The proper choice, consequently, of a Clock Distribution network is not dictated by a single design objective but rather by the overall 3-D system design requirements including availability of resources and number of bonded planes.
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delay uncertainty in high performance Clock Distribution Networks
2010Co-Authors: Dimitrios Velenis, Eby G FriedmanAbstract:The continuous quest for higher circuit performance has pushed Clock frequencies deep into the gigahertz frequencies range, reducing the period of the Clock signal well below a nanosecond. The resulting constraints demonstrate the requirement for tight timing control of the arrival times of the Clock signal at the many Clocked elements throughout an integrated circuit. In this book, a design methodology for enhancing the tolerance of a circuit to the uncertainty of the Clock signal delay is presented. This methodology either relaxes the timing constraints at the most critical data paths, or reduces the delay uncertainty among the Clock signals that synchronize these paths. Power tradeoffs of the proposed design techniques are investigated and physical layout information is incorporated to synthesize the Clock tree layout based on a set of benchmark circuits. This book provides the reader with information on those effects that introduce delay uncertainty and with the tools to successfully design high performance synchronous circuits. The original research presented in this book has been awarded with the Outstanding Dissertation Award by the European Design Automation Association.
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Clock and power Distribution Networks for 3 d ics
Design Automation and Test in Europe, 2009Co-Authors: Ioannis Savidis, Eby G Friedman, Vasileios Pavlidis, Giovanni De MicheliAbstract:Global interconnect design for threedimensional integrated circuits is a crucial task. Despitethe importance of this task, limited results related to global issues have been presented. Challenges in reliably distributing power, ground, and the Clock signal within a multi-plane integrated system are discussed in this paper. The design of two 3-D test circuits addressing these issues is described. Candidate 3-D topologies for both power and Clock Distribution Networks are also presented. Design implications due to the different design approaches are discussed. Experimental and simulation results of the 3-D Clock and power Distribution architectures, respectively, are provided. Both of the test circuits are fabricated by the 3-D fabrication process developed at MIT Lincoln Laboratories (MITLL). The design of the Clock and power Distribution Networks is discussed
Jose Roberto Castilho Piqueira - One of the best experts on this subject based on the ideXlab platform.
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architectures stability and optimization for Clock Distribution Networks
Communications in Nonlinear Science and Numerical Simulation, 2012Co-Authors: Rodrigo Carareto, Fernando Moya Orsatti, Jose Roberto Castilho PiqueiraAbstract:Synchronous telecommunication Networks, distributed control systems and integrated circuits have its accuracy of operation dependent on the existence of a reliable time basis signal extracted from the line data stream and acquirable to each node. In this sense, the existence of a sub-network (inside the main network) dedicated to the Distribution of the Clock signals is crucially important. There are different solutions for the architecture of the time Distribution sub-network and choosing one of them depends on cost, precision, reliability and operational security. In this work we expose: (i) the possible time Distribution Networks and their usual topologies and arrangements. (ii) How parameters of the network nodes can affect the reachability and stability of the synchronous state of a network. (iii) Optimizations methods for synchronous Networks which can provide low cost architectures with operational precision, reliability and security.
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design constraints for third order pll nodes in master slave Clock Distribution Networks
Communications in Nonlinear Science and Numerical Simulation, 2010Co-Authors: Atila Madureira Bueno, A G Rigon, A A Ferreira, Jose Roberto Castilho PiqueiraAbstract:Clock signal Distribution in telecommunication commercial systems usually adopts a master-slave architecture, with a precise time basis generator as a master and phase-locked loops (PLLs) as slaves. In the majority of the Networks, second-order PLLs are adopted due to their simplicity and stability. Nevertheless, in some applications better transient responses are necessary and, consequently, greater order PLLs need to be used, in spite of the possibility of bifurcations and chaotic attractors. Here a master-slave network with third-order PLLs is analyzed and conditions for the stability of the synchronous state are derived, providing design constraints for the node parameters, in order to guarantee stability and reachability of the synchronous state for the whole network. Numerical simulations are carried out in order to confirm the analytical results.
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comparing lock in ranges and transient responses of second and third order phase locked loops in master slave Clock Distribution Networks
Aeu-international Journal of Electronics and Communications, 2008Co-Authors: Jose Roberto Castilho Piqueira, Marcela De Carvalho FreschiAbstract:Abstract The Distribution of Clock signals throughout the nodes of a network is essential for several applications in control and communication with the phase-locked loop (PLL) being the component for electronic synchronization process. In systems with master–slave (MS) strategies, the PLLs are the slave nodes responsible for providing reliable Clocks in all nodes of the network. As PLLs have nonlinear phase detection, double-frequency terms appear and filtering becomes necessary. Imperfections in filtering process cause oscillations around the synchronous state worsening the performance of the Clock Distribution process. The behavior of one-way master–slave (OWMS) Clock Distribution Networks is studied and performances of first- and second-order filter processes are compared, concerning lock-in ranges and responses to perturbations of the synchronous state.
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models for master slave Clock Distribution Networks with third order phase locked loops
Mathematical Problems in Engineering, 2007Co-Authors: Jose Roberto Castilho Piqueira, Marcela De Carvalho FreschiAbstract:The purpose of this work is to study the processing and transmission of Clock signals in Networks of geographically distributed nodes, in order to derive conditions for frequency and phase synchronization between the nodes. The focus is on the master-slave architecture, which presents a priority scheme of Clock Distribution. One-way master-slave (OWMS ) and two-way master-slave (TWMS) chains are studied, considering that the slave nodes are third-order phase-locked loops (PLLs). Third-order PLLs are chosen to improve the transient response but, if their parameters are not well adjusted, stability problems and chaotic behaviors appear, restricting the lock-in range of the network. Lock-in range for third-order PLLs with Sallen-Key filter is determined and it is verified whether this range is reduced when the PLLs are connected to a network. Numerical experiments show how chain size changes the lock-in ranges and the acquisition times.
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double frequency jitter in chain master slave Clock Distribution Networks comparing topologies
Journal of Communications and Networks, 2006Co-Authors: Jose Roberto Castilho Piqueira, Andrea Zaneti CaligaresAbstract:Master-slave (M-S) strategies implemented with chain circuits are the main option in order to distribute Clock signals along synchronous Networks in several telecommunication and control applications. Here, we study the two types of master-slave chains: Without Clock feedback, i.e., one-way master-slave (OWMS) and with Clock feedback, i.e., two-way master-slave (TWMS) considering the slave nodes as second-order phase-locked loops (PLL) for several types of loop low-pass filters.
Dimitrios Velenis - One of the best experts on this subject based on the ideXlab platform.
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delay uncertainty in high performance Clock Distribution Networks
2010Co-Authors: Dimitrios Velenis, Eby G FriedmanAbstract:The continuous quest for higher circuit performance has pushed Clock frequencies deep into the gigahertz frequencies range, reducing the period of the Clock signal well below a nanosecond. The resulting constraints demonstrate the requirement for tight timing control of the arrival times of the Clock signal at the many Clocked elements throughout an integrated circuit. In this book, a design methodology for enhancing the tolerance of a circuit to the uncertainty of the Clock signal delay is presented. This methodology either relaxes the timing constraints at the most critical data paths, or reduces the delay uncertainty among the Clock signals that synchronize these paths. Power tradeoffs of the proposed design techniques are investigated and physical layout information is incorporated to synthesize the Clock tree layout based on a set of benchmark circuits. This book provides the reader with information on those effects that introduce delay uncertainty and with the tools to successfully design high performance synchronous circuits. The original research presented in this book has been awarded with the Outstanding Dissertation Award by the European Design Automation Association.
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Parameter variations and crosstalk noise effects on high performance H-tree Clock Distribution Networks
Analog Integrated Circuits and Signal Processing, 2008Co-Authors: I. Chanodia, Dimitrios VelenisAbstract:Controlling the delay and the transition time of the Clock signal in the presence of various noise sources, process parameter variations and environmental effects represents a fundamental problem in the design of high speed synchronous circuits. The effects of parameter variations and crosstalk noise on the Clock signal propagating along an H-tree Clock Distribution network are investigated in this paper. In particular, the effects of variations in power supply voltage ( V _DD), temperature, and gate oxide thickness ( t _ox) on the delay and the transition time of the Clock signal are evaluated. Furthermore, the effects of crosstalk between an H-tree structure and other interconnect wires are investigated. Different scenarios of capacitive coupling along different spatial locations of an H-tree are considered. The effects of coupling on the propagation delay, the transition time, and the waveform shape of the Clock signal are demonstrated.
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effects of crosstalk noise on h tree Clock Distribution Networks
International Symposium on Circuits and Systems, 2006Co-Authors: I. Chanodia, Dimitrios VelenisAbstract:With the transition to deep submicron technologies the density of on-chip interconnect lines has increased, together with the switching rate of the signals propagating along these lines, resulting in increased on-chip interconnect noise. The effects of crosstalk noise on the Clock signal propagation along an H-tree Clock Distribution network are investigated in this paper. Different scenarios of capacitive coupling along different spatial locations of an H-tree are considered. The effects of coupling on the propagation delay, the transition time, and the waveform shape of the Clock signal are investigated.
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Effects of parameter variations and crosstalk noise on H-tree Clock Distribution Networks
IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06), 2006Co-Authors: I. Chanodia, Dimitrios VelenisAbstract:The effects of parameter variations and crosstalk noise on the Clock signal propagating along an H-tree Clock Distribution network are investigated in this paper. In particular, the effects of variations in power supply voltage (VDD), and temperature on the delay and the transition time of the Clock signal are evaluated. Furthermore, the effects of crosstalk between an H-tree structure and other interconnect wires are investigated. Different scenarios of capacitive coupling along different spatial locations of an H-tree are considered. The effects of coupling on the propagation delay, the transition time, and the waveform shape of the Clock signal are demonstrated
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Effects of parameter variations and crosstalk on H-tree Clock Distribution Networks
48th Midwest Symposium on Circuits and Systems 2005., 2005Co-Authors: I. Chanodia, Dimitrios VelenisAbstract:Controlling the delay and the transition time of the Clock signal in the presence of various noise sources, process parameter variations and environmental effects represents a fundamental problem in the design of high speed synchronous circuits. The effects of parameter variations and crosstalk noise on the Clock signal propagating along an H-tree Clock Distribution network are investigated in this paper. In particular, the effects of variations in power supply (VDD), temperature, and gate oxide thickness (tOX) on the Clock signal delay and transition time are evaluated. In addition to parameter variations, crosstalk effects among the H-tree structure and other interconnect wires are investigated. It is shown that the delay and transition time of the Clock signal is spatially dependent on interconnect crosstalk along an H-tree
Vasilis F. Pavlidis - One of the best experts on this subject based on the ideXlab platform.
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case study Clock Distribution Networks for three dimensional ics
Three-Dimensional Integrated Circuit Design (Second Edition), 2017Co-Authors: Vasilis F. Pavlidis, Ioannis Savidis, Eby G FriedmanAbstract:A prototype circuit, the second of the three prototype circuits presented in this book, investigating different global three-dimensional (3-D) Clock Distribution Networks, is described in this chapter. A variety of Clock Networks such as H-trees, rings, tree-like Networks, and trunk-based Networks, are explored in terms of Clock skew and power consumption to determine an effective Clock Distribution network for 3-D ICs. The prototype test circuit composed of these Networks is manufactured by the 3-D fabrication process developed at MIT Lincoln Laboratories. The design and modeling process and related experimental results are also included in this chapter. Power and Clock skew tradeoffs among the different topologies are presented.
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low power Clock Distribution Networks for 3 d ics
IEEE Convention of Electrical and Electronics Engineers in Israel, 2012Co-Authors: Somayyeh Rahimian, Giovanni De Micheli, Vasilis F. PavlidisAbstract:Designing a low power Clock network in synchronous circuits is an important task. This requirement is stricter for 3-D circuits due to the increased power densities. Resonant Clock Networks are considered efficient low-power alternatives to conventional Clock Distribution schemes. These Networks utilize additional inductive circuits to reduce the power consumption while delivering a full swing Clock signal to the sink nodes. Test is another complex task for 3-D ICs, where pre-bond test is a prerequisite. This paper, consequently, introduces a design methodology for resonant 3-D Clock Networks that lowers the power of the Clock Networks while supporting pre-bond test. Several 3-D Clock network topologies are explored in a 0.18 μm CMOS technology. Simulation results indicate 43% reduction in the power consumed by the resonant 3-D Clock network as compared to a conventional buffered Clock network. By properly distributing the inductance within the layers of the 3-D stack, resonance is ensured both in pre-bond test and normal operation. The important aspects of this approach are introduced in this paper.
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effect of process variations in 3d global Clock Distribution Networks
ACM Journal on Emerging Technologies in Computing Systems, 2012Co-Authors: Vasilis F. Pavlidis, Giovanni De MicheliAbstract:In three-dimensional (3D) integrated circuits, the effect of process variations on Clock skew differs from 2D circuits. The combined effect of inter-die and intra-die process variations on the design of 3D Clock Distribution Networks is considered in this article. A statistical Clock skew model incorporating both the systematic and random components of process variations is employed to describe this effect. Two regular 3D Clock tree topologies are investigated and compared in terms of Clock skew variation. The statistical skew model used to describe Clock skew variations is verified through Monte-Carlo simulations. The Clock skew is shown to change in different ways with the number of planes forming the 3D IC and the Clock network architecture. Simulations based on a 45-nm CMOS technology show that the maximum standard deviation of Clock skew can vary from 15 ps to 77 ps. Results indicate that simply increasing the number of planes of a 3D IC does not necessarily lead to lower skew variation and higher operating frequencies. A multigroup 3D Clock tree topology is proposed to effectively mitigate the variability of Clock skew. Tradeoffs between the investigated 3D Clock Distribution Networks and the number of planes comprising a 3D circuit are discussed and related design guidelines are offered. The skew variation in 3D Clock trees is also compared with the skew variation of Clock grids.
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the combined effect of process variations and power supply noise on Clock skew and jitter
International Symposium on Quality Electronic Design, 2012Co-Authors: Hu Xu, Vasilis F. Pavlidis, Wayne Burleson, Giovanni De MicheliAbstract:In modern VLSI circuits, a large number of Clock buffers are inserted in Clock Distribution Networks, which are significantly affected by process and power supply noise variations. The combined effect of process variations and power supply noise on Clock skew and jitter is investigated in this paper. A statistical model of skitter, which consists of skew and jitter, is proposed. Clock paths with different buffer insertion strategies are compared in terms of skew and jitter. The tradeoffs among the constraints on Clock jitter, skew, slew rate, and power are discussed. For strict timing constraints, severe power overhead (≥ 110%) has to be added to obtain a low improvement in the worst case skitter and slew rate (≤ 13%). The effect of widely-used techniques, such as recombinant trees and dynamic voltage scaling, on decreasing skitter is also investigated.
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a low overhead method for pre bond test of resonant 3 d Clock Distribution Networks
IEEE 3rd International Worksh op on Testing Three - Dimensional Stacked Integrated Circuits (3D-Test), 2012Co-Authors: Somayyeh Rahimian, Vasilis F. Pavlidis, Giovanni De MicheliAbstract:Designing a low power Clock network in synchronous circuits is an important task. This requirement is stricter for 3-D circuits due to the increased power densities. Resonant Clock Networks are considered efficient low power alternatives to con- ventional Clock Distribution schemes. These Networks utilize ad- ditional inductive circuits to reduce power while delivering a full swing Clock signal to the sink nodes. Test is another complex task for 3-D ICs, where pre-bond test is a prerequisite. Contactless test has been considered as an alternative for conventional test methods. This paper, consequently, introduces a design method- ology for resonant 3-D Clock Networks that supports wireless pre- bond testing through the use of inductive links. By employing the inductors comprising the LC tanks of the resonant Clock net- works as the receiver circuit for the links, the need for additional circuits and/or interconnect resources during pre-bond test is essentially eliminated. The proposed technique produces low power and pre-bond testable 3-D Clock Distribution Networks. Simulation results indicate 98.5% and 99% decrease in the area overhead and power consumed by the contactless testing method as compared to existing methods.
Glenn Cowan - One of the best experts on this subject based on the ideXlab platform.
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dual edge triggered sense amplifier flip flop for resonant Clock Distribution Networks
Iet Computers and Digital Techniques, 2010Co-Authors: S E Esmaeili, A J Alkhalili, Glenn CowanAbstract:A dual-edge sense amplifier flip-flop (DE-SAFF) for resonant Clock Distribution Networks (CDNs) is proposed. The Clocking scheme used to enable dual-edge triggering in the proposed SAFF reduces short circuit power by allowing the precharging transistors to be switched on only for a portion of the Clock period. The extracted circuit layout of the proposed DE-SAFF has been simulated in STMicroelectronics 90 nm technology with a resonant Clock signal at a frequency of 500 MHz. Simulation results show correct functionality of the flip-flip under process, voltage and temperature variations. Two low-power Clocking techniques, the dual-edge triggering method and the emerging resonant (sinusoidal) Clocking technique, have been combined to enable further power reduction in the CDN. Modelling the resonant Clock Distribution system with the proposed flip-flop illustrates that dual-edge triggering can achieve up to 58% reduction in the power consumption of resonant Clock Networks.
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skew compensation in energy recovery Clock Distribution Networks
Iet Computers and Digital Techniques, 2010Co-Authors: S E Esmaeili, Ali M Farhangi, A J Alkhalili, Glenn CowanAbstract:In this study a new approach for skew compensation in energy recovery Clock Distribution Networks is introduced by manipulating the operating speed of the flip-flops. The STMicroelectronics 90 nm technology allows the use of devices with different threshold voltages, namely: high threshold voltage (HVT), standard threshold voltage (SVT) and low threshold voltage (LVT). Three types of flip-flops of equal input load: fast , standard and slow are used. Timing parameters of the flip-flops are adjusted by manipulating the switching threshold of the Clock port of the flip-flops. A fast/slow flip-flop has a shorter/longer T DQ delay, compared with a standard flip-flop for the same setup time (T DCLK ). Distributing flip-flops according to their delay requirements would reduce the effect of the Clock's skew on the outputs of sequentially adjacent flip-flops. Owing to the slow rise time of the sinusoidal Clock signal used in energy recovery Clock Distribution Networks compared to the conventional square-wave Clock, the skew that can be compensated for in energy recovery Clock Distribution Networks using this approach would be much higher than in square-wave Clock Distribution Networks. This approach increases the skew bounds required by algorithms to balance the skew in the Clock tree leading to reduced design complexity. Theoretical analysis and simulation results using STMicroelectronics 90 nm technology at a Clock frequency of 500 MHz show that this approach is feasible and effective where a skew of up to 6.2% 1of the Clock period can be compensated for in the example used. In addition, constructing Clock trees using the skew slack provided in the proposed technique in a new modified differed merge embedding (DME) algorithm on five benchmarks have shown that the proposed technique enables an average reduction of 11.5% in total wire length and 53.2% reduction in the number of wire elongations. Balancing the skew in the Clock tree using buffers was not considered here since inserting a buffer in the Clock's path eliminates the energy recovery property. As an example of illustrating the proposed methodology, the authors have used the Elmore delay model with a selected energy recovery flip-flop to verify the practicality of the proposed scheme. Better results can be obtained by using different flip-flops. The method can generally be applied to energy recovery or square-wave Clocking if different flip-flops of various speeds are used.
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a novel approach for skew compensation in energy recovery Clock Distribution Networks
International Conference on Microelectronics, 2008Co-Authors: S E Esmaeili, A J Alkhalili, Glenn CowanAbstract:In this paper a new approach for skew compensation in energy recovery Clock Distribution Networks is introduced by manipulating the operating speed of the flip-flops. Three types of flip-flops: ?fast?, ?standard?, and ?slow? are used. Distributing flip-flops according to their delay requirements would reduce the effect of the Clock's skew on the outputs of sequentially adjacent flip-flops. This approach increases the skew bounds required by algorithms to balance the skew in the Clock Distribution network leading to reduced design complexity. Theoretical analysis and simulation results at a Clock frequency of 500 MHz show that this approach is feasible and effective where a skew of up to 6.2% of the Clock period can be compensated for.