The Experts below are selected from a list of 40236 Experts worldwide ranked by ideXlab platform
Keith Bowman - One of the best experts on this subject based on the ideXlab platform.
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a unified Clock and switched capacitor based power delivery architecture for variation tolerance in low voltage soc domains
IEEE Journal of Solid-state Circuits, 2019Co-Authors: Fahim Ur Rahman, Keith Bowman, Naveen John, Roshan Kumar, Rajesh Pamula, Xi Li, Visvesh S SatheAbstract:Correctly operating digital SoC domains at their target frequencies require the addition of supply voltage ( $V_{\mathrm{ dd}}$ ) guardbands to account for supply droop events and temperature variation. These guardbands degrade processor energy efficiency, especially in low-voltage sensor and IoT applications due to increased delay sensitivity to temperature and $V_{\mathrm{ dd}}$ variation. In this paper, we present an all-digital unified Clock and power (UniCaP-SC) architecture that combines switched-capacitor (SC)-based voltage control and Clock Frequency regulation into a single loop to significantly reduce required $V_{\mathrm{ dd}}$ guardbands. A UniCaP-SC test chip consisting of a near-threshold voltage (NTV) ARM Cortex-M0 processor was fabricated in 65-nm CMOS. The fully integrated system enables all-digital construction, aggressive $V_{\mathrm{ dd}}$ margin reduction, and continuous $V_{\mathrm{ dd}}$ scalability using SC-based voltage converters while no additional decoupling capacitance (decap). Test-chip measurements demonstrate a 16% $V_{\mathrm{ dd}}$ reduction corresponding to a 94% $V_{\mathrm{ dd}}$ margin recovery or an equivalent $3.2\times $ increase in the operating Clock Frequency ( $f_{\mathrm{ clk}}$ ).
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an all digital unified Clock Frequency and switched capacitor voltage regulator for variation tolerance in a sub threshold arm cortex m0 processor
Symposium on VLSI Circuits, 2018Co-Authors: Fahim Ur Rahman, Keith Bowman, Sung Kim, Naveen John, Roshan Kumar, Rajesh Pamula, Visvesh S SatheAbstract:An all-digital switched-capacitor (SC) based Clock Frequency (Felk) and supply voltage (V dd) regulator unifies Fclk and Vdd generation into a single control loop to reduce the V dd margin for variations in a sub-threshold ARM Cortex M0 processor. This fully-integrated unified Clock and power (Uni-CaP) architecture allows continuous Vdd scalability without a low-dropout (LDO) regulator. Measurements from a 65nm test chip demonstrate a 16% Vdd reduction (94% Vdd margin recovery) and a 3.2× increase in Fclk operating range.
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energy efficient and metastability immune timing error detection and recovery circuits for dynamic variation tolerance
International Conference on IC Design and Technology, 2008Co-Authors: Keith Bowman, J Tschanz, Nam Sung Kim, Jongsun Lee, Christopher B Wilkerson, Tanay KarnikAbstract:Timing-error detection and recovery circuits are implemented in a 65 nm resilient circuit test-chip to eliminate the Clock Frequency guardband from dynamic supply voltage (VCC) and temperature variations as well as to exploit path-activation probabilities for maximizing throughput. Two error-detection sequential (EDS) circuits are introduced to preserve the timing-error detection capability of previous EDS designs while lowering Clock energy and removing datapath metastability. Error-recovery circuits replay failing instructions at lower Clock Frequency to guarantee correct functionality. Relative to conventional circuits, silicon measurements indicate that resilient circuits enable either 25 to 32% throughput gain at equal VCC or at least 17% VCC reduction at equal throughput, resulting in 31 to 37% total power reduction.
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impact of die to die and within die parameter fluctuations on the maximum Clock Frequency distribution for gigascale integration
IEEE Journal of Solid-state Circuits, 2002Co-Authors: Keith Bowman, S.g. DuvallAbstract:A model describing the maximum Clock Frequency (FMAX) distribution of a microprocessor is derived and compared with wafer sort data for a recent 0.25-/spl mu/m microprocessor. The model agrees closely with measured data in mean, variance, and shape. Results demonstrate that within-die fluctuations primarily impact the FMAX mean and die-to-die fluctuations determine the majority of the FMAX variance. Employing rigorously derived device and circuit models, the impact of die-to-die and within-die parameter fluctuations on future FMAX distributions is forecast for the 180, 130, 100, 70, and 50-nm technology generations. Model predictions reveal that systematic within-die fluctuations impose the largest performance degradation resulting from parameter fluctuations. Assuming a 3/spl sigma/ channel length deviation of 20%, projections for the 50-nm technology generation indicate that essentially a generation of performance gain can be lost due to systematic within-die fluctuations. Key insights from this work elucidate the recommendations that manufacturing process controls be targeted specifically toward sources of systematic within-die fluctuations, and the development of new circuit design methodologies be aimed at suppressing the effect of within-die parameter fluctuations.
Takayasu Sakurai - One of the best experts on this subject based on the ideXlab platform.
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intermittent resonant Clocking enabling power reduction at any Clock Frequency for near sub threshold logic circuits
IEEE Journal of Solid-state Circuits, 2014Co-Authors: Hiroshi Fuketa, Makoto Takamiya, Masahiro Nomura, Takayasu SakuraiAbstract:In order to eliminate the limitation of a narrow Frequency range of conventional resonant Clocking, intermittent resonant Clocking (IRC) is proposed for near/sub-threshold logic circuits. In this paper, IRC is applied to 0.37 V 32-bit adder array with latches and adder array with flip-flops fabricated in a 40 nm CMOS process. Measurement results show that IRC reduces the Clock power by 36% at 980 kHz and the Clock leakage power by 81% compared with conventional non-resonant Clocking when IRC is applied to the adder array with latches. The same power reduction is achieved when IRC is applied to the adder array with flip-flops. IRC can reduce the Clock power at any Clock Frequency, which enables flexible selection of the Clock Frequency.
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intermittent resonant Clocking enabling power reduction at any Clock Frequency for 0 37v 980khz near threshold logic circuits
International Solid-State Circuits Conference, 2013Co-Authors: Hiroshi Fuketa, Makoto Takamiya, Masahiro Nomura, Takayasu SakuraiAbstract:In order to improve the energy efficiency of logic circuits, reductions in capacitance (C) and power supply voltage (VDD) are required, as energy consumption is proportional to CVDD2. Near-threshold (Vt) operation achieves an energy minimum. Resonant Clocking can reduce the effective capacitance of the Clock distribution network. In this work, a new resonant Clocking scheme enabling power reduction at any Clock Frequency is proposed and applied to a 0.37V 980kHz near-Vt logic circuit in 40nm CMOS.
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switched resonant Clocking src scheme enabling dynamic Frequency scaling and low speed test
Custom Integrated Circuits Conference, 2009Co-Authors: Katsuyuki Ikeuchi, Kosuke Sakaida, Takayasu Sakurai, Koichi Ishida, Makoto TakamiyaAbstract:A novel Switched Resonant Clocking (SRC) scheme is proposed to solve two basic problems of the conventional resonant Clocking, that is, power increase and Clock waveform inability at the lower Clock Frequency region. The power increase prohibits widely-used dynamic Frequency scaling (DFS) and the waveform instability hinders low-speed function tests. A test chip in 0.18μm CMOS is manufactured and measured to show that the SRC suppresses power increase at low Clock Frequency and enables the low-speed tests, while reducing the Clock power by 8% at 1.5-GHz Clock with an area penalty of 4.8%.
Visvesh S Sathe - One of the best experts on this subject based on the ideXlab platform.
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a unified Clock and switched capacitor based power delivery architecture for variation tolerance in low voltage soc domains
IEEE Journal of Solid-state Circuits, 2019Co-Authors: Fahim Ur Rahman, Keith Bowman, Naveen John, Roshan Kumar, Rajesh Pamula, Xi Li, Visvesh S SatheAbstract:Correctly operating digital SoC domains at their target frequencies require the addition of supply voltage ( $V_{\mathrm{ dd}}$ ) guardbands to account for supply droop events and temperature variation. These guardbands degrade processor energy efficiency, especially in low-voltage sensor and IoT applications due to increased delay sensitivity to temperature and $V_{\mathrm{ dd}}$ variation. In this paper, we present an all-digital unified Clock and power (UniCaP-SC) architecture that combines switched-capacitor (SC)-based voltage control and Clock Frequency regulation into a single loop to significantly reduce required $V_{\mathrm{ dd}}$ guardbands. A UniCaP-SC test chip consisting of a near-threshold voltage (NTV) ARM Cortex-M0 processor was fabricated in 65-nm CMOS. The fully integrated system enables all-digital construction, aggressive $V_{\mathrm{ dd}}$ margin reduction, and continuous $V_{\mathrm{ dd}}$ scalability using SC-based voltage converters while no additional decoupling capacitance (decap). Test-chip measurements demonstrate a 16% $V_{\mathrm{ dd}}$ reduction corresponding to a 94% $V_{\mathrm{ dd}}$ margin recovery or an equivalent $3.2\times $ increase in the operating Clock Frequency ( $f_{\mathrm{ clk}}$ ).
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an all digital unified Clock Frequency and switched capacitor voltage regulator for variation tolerance in a sub threshold arm cortex m0 processor
Symposium on VLSI Circuits, 2018Co-Authors: Fahim Ur Rahman, Keith Bowman, Sung Kim, Naveen John, Roshan Kumar, Rajesh Pamula, Visvesh S SatheAbstract:An all-digital switched-capacitor (SC) based Clock Frequency (Felk) and supply voltage (V dd) regulator unifies Fclk and Vdd generation into a single control loop to reduce the V dd margin for variations in a sub-threshold ARM Cortex M0 processor. This fully-integrated unified Clock and power (Uni-CaP) architecture allows continuous Vdd scalability without a low-dropout (LDO) regulator. Measurements from a 65nm test chip demonstrate a 16% Vdd reduction (94% Vdd margin recovery) and a 3.2× increase in Fclk operating range.
Yuwei Yang - One of the best experts on this subject based on the ideXlab platform.
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temperature aware dynamic Frequency and voltage scaling for reliability and yield enhancement
Asia and South Pacific Design Automation Conference, 2009Co-Authors: Yuwei Yang, Katherine Shumin LiAbstract:A novel oscillation-based on-chip thermal sensing architecture for dynamically adjusting supply voltage and Clock Frequency in System-on-Chip (SoC) is proposed. It is shown that the oscillation Frequency of a ring oscillator reduces linearly as the temperature rises, and thus provides a good on-chip temperature sensing mechanism. An efficient Dynamic Frequency-to-Voltage Scaling (DF2VS) algorithm is proposed to dynamically adjust supply voltage according to the oscillation frequencies of the ring oscillators distributed in SoC so that thermal sensing can be carried at all potential hot spots. An on-chip Dynamic Voltage Scaling or Dynamic Voltage and Frequency Scaling (DVS or DVFS) monitor selects the supply voltage level and Clock Frequency according to the outputs of all thermal sensors. Experimental results on SoC benchmark circuits show the effectiveness of the algorithm that a 10% reduction in supply voltage alone can achieve about 20% power reduction (DVS scheme), and nearly 50% reduction in power is achievable if the Clock Frequency is also scaled down (DVFS scheme). The chip temperature is reduced accordingly.
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temperature aware dynamic Frequency and voltage scaling for reliability and yield enhancement
Asia and South Pacific Design Automation Conference, 2009Co-Authors: Yuwei YangAbstract:A novel oscillation-based on-chip thermal sensing architecture for dynamically adjusting supply voltage and Clock Frequency in System-on-Chip (SoC) is proposed. It is shown that the oscillation Frequency of a ring oscillator reduces linearly as the temperature rises, and thus provides a good on-chip temperature sensing mechanism. An efficient Dynamic Frequency-to-Voltage Scaling (DF2VS) algorithm is proposed to dynamically adjust supply voltage according to the oscillation frequencies of the ring oscillators distributed in SoC so that thermal sensing can be carried at all potential hot spots. An on-chip Dynamic Voltage Scaling or Dynamic Voltage and Frequency Scaling (DVS or DVFS) monitor selects the supply voltage level and Clock Frequency according to the outputs of all thermal sensors. Experimental results on SoC benchmark circuits show the effectiveness of the algorithm that a 10% reduction in supply voltage alone can achieve about 20% power reduction (DVS scheme), and nearly 50% reduction in power is achievable if the Clock Frequency is also scaled down (DVFS scheme). The chip temperature is reduced accordingly.
E K F Lee - One of the best experts on this subject based on the ideXlab platform.
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a low power segmented nonlinear dac based direct digital Frequency synthesizer
IEEE Journal of Solid-state Circuits, 2002Co-Authors: Jiandong Jiang, E K F LeeAbstract:A 2.5-V CMOS direct digital Frequency synthesizer (DDFS) with 12 bits of phase resolution and 11 bits of amplitude resolution is presented. Low power consumption is achieved using a nonlinear digital-to-analog converter (DAC). To further reduce power and area, a new technique is proposed to segment the non-linear DAC into a coarse nonlinear DAC and a number of fine nonlinear sub-DACs. The DDFS fabricated in a 0.25-/spl mu/m CMOS process occupies an active area of 1.4 mm/sup 2/. For a Clock Frequency of 300 MHz, it consumes 240 mW and the spurious-free dynamic range is less than 51 dB for output frequencies up to 3/8 of the Clock Frequency.
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a rom less direct digital Frequency synthesizer using segmented nonlinear digital to analog converter
Custom Integrated Circuits Conference, 2001Co-Authors: Jiandong Jiang, E K F LeeAbstract:A direct digital Frequency synthesizer (DDFS) based on nonlinear digital-to-analog converter (DAC) is presented. A new technique is proposed to segment the nonlinear DAC such that high speed DDFS with low power consumption and small die area can be achieved. The DDFS has 12 bits of phase resolution and 11 bits of magnitude resolution. It was fabricated in a 0.25 /spl mu/m CMOS process with an active area of 1.4 mm/sup 2/. For a Clock Frequency of 300 MHz, the spurious free dynamic range (SFDR) is better than 50 dB with output frequencies up to 3/8 of the Clock Frequency.