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Byung-gook Park - One of the best experts on this subject based on the ideXlab platform.

  • an accurate and stable humidity sensing characteristic of si fet type humidity sensor with mos 2 as a sensing layer by pulse measurement
    Sensors and Actuators B-chemical, 2018
    Co-Authors: Jongmin Shin, Yoonki Hong, Meile Wu, Hyuckin Kwon, Byung-gook Park
    Abstract:

    Abstract In this work, we demonstrate the pulse scheme to obtain stable humidity sensing characteristics in Si FET-type humidity sensor using MoS2 film as a sensing layer. To investiGate the reaction between H2O molecules and MoS2 film, the transfer characteristics (ID-VCG) and transient drain current behaviors (ID-t) are measured in both pMOSFET and nMOSFET sensors by DC measurement. To verify the effect of the pulse scheme, the pulsed I–V (PIV) and the ID-t are measured as a parameter of relative humidity. The ID drift of the FET-type sensor is effectively eliminated by applying the pulse to the Control-Gate (CG) of the FET-type humidity sensor.

  • fabrication and characteristics of self aligned dual Gate single electron transistors
    IEEE Transactions on Nanotechnology, 2009
    Co-Authors: Dong Seup Lee, Dong Myong Kim, Jong Duk Lee, Sangwoo Kang, Kwonchil Kang, Joungeob Lee, Junghoon Lee, Kwanjae Song, Byung-gook Park
    Abstract:

    Single-electron transistors that have electrical tunneling barriers are fabricated, and Coulomb oscillation peaks and negative differential transconductance are observed at room temperature (300 K). Operation characteristics and multioscillation peaks are further investiGated at low temperature (80 K). The period of Coulomb oscillation is 2.3 V due to an ultrasmall Control Gate capacitance, and oscillation peaks are shifted through the side Gate bias, which is explained by the derived stability plot for dual-Gate structures. Even with the side Gates electrically floating, the device still operates as a single-electron transistor since the p-n junction barrier plays a role of tunneling barrier. In addition, by changing the bias condition, double dots are formed along the channel and peak splitting is observed.

  • self aligned dual Gate single electron transistors
    Japanese Journal of Applied Physics, 2008
    Co-Authors: Sangwoo Kang, Dae Hwan Kim, Jong Duk Lee, Joungeob Lee, Ilhan Park, Jinho Kim, Byung-gook Park
    Abstract:

    A novel complementary metal–oxide–semiconductor (CMOS) process compatible and self-aligned fabrication method for the dual-Gate single-electron transistor (DG-SET) is presented. The performance of previous versions of the DG-SET was limited by inherent parasitic elements and its fabrication process was divergent from conventional CMOS, limiting the possibility of co-integration. Through simulation, the parasitic elements are confirmed to be caused by the non-self-alignment of the Control Gate, side Gates, and source/drain. To resolve such issues, a new type of DG-SET was fabricated using a self-aligned process. Measurement results obtained at room temperature revealed clear Coulomb oscillation peaks in the trans-conductance curve. Through parameter extraction and its comparison with previous results, this is confirmed to be the consequence of single-electron tunneling. Also, in order to confirm that the single-electron tunneling is caused by the electrically induced tunneling barriers, and not by random fluctuations along the SOI active, low temperature measurement results for devices with different parameters is compared.

  • twin sonos memory with 30 nm storage nodes under a merged Gate fabricated with inverted sidewall and damascene process
    IEEE Electron Device Letters, 2004
    Co-Authors: Yongkyu Lee, Byung-gook Park, Ki Whan Song, Jae Woong Hyun, Jong Duk Lee, Sung Taeg Kang, Jeong Dong Choe, Sang Yeon Han, Jeong Nam Han, Sung Woo Lee
    Abstract:

    By manipulating the charge profile through the inverted sidewall patterning on the channel, stable 2-bit operation in silicon-oxide-nitride-oxide-silicon (SONOS) Flash memory with sub-90-nm Gate length can be achieved. The fabricated memory cell has about 30-nm twin Oxide-Nitride-Oxide-Silicon physically separated by the inverted sidewall patterning method under the same Control Gate based on damascene Gate process. Comparing with a conventional single SONOS memory (SSM), this novel twin SONOS memory cell can maintain the better Control of trapped charge distribution due to the strong diffusion barrier of charges. As a result, better endurance, retention, and erase speed than SSM can be obtained in the short (sub-100-nm) Gate length devices.

  • twin bit silicon oxide nitride oxide silicon sonos memory by inverted sidewall patterning tsm isp
    IEEE Silicon Nanoelectronics Workshop, 2003
    Co-Authors: Yongkyu Lee, Jong Duk Lee, Tae Hun Kim, Sanghoon Lee, Byung-gook Park
    Abstract:

    We have proposed a new twin-bit silicon-oxide-nitride-oxide-silicon memory (TSM)-inverted sidewall patterning (ISP) cell which has twin oxide-nitride-oxides (ONOs) physically separated by the ISP method under one Control Gate. This TSM-ISP can Control the trapped charge distribution and make diffusion barrier of charges, so that program/erase (P/E) endurance and retention can be increased. The trapping nitride is narrow enough to reduce hot-hole erase times. To estimate the new device characteristics, we have devised a special simulation method of silicon-oxide-nitride-oxide-silicon (SONOS) by implementing a simple idea in the conventional device simulator, "MEDICI." By placing the floating nodes in nitride with adjusted density, which is supposed to play the role of charge traps in nitride, we can estimate not only the conventional SONOS characteristics, but also the new SONOS characteristics, such as TSM-ISP.

Lei Deng - One of the best experts on this subject based on the ideXlab platform.

  • gxnor net training deep neural networks with ternary weights and activations without full precision memory under a unified discretization framework
    Neural Networks, 2018
    Co-Authors: Lei Deng, Peng Jiao, Jing Pei
    Abstract:

    Although deep neural networks (DNNs) are being a revolutionary power to open up the AI era, the notoriously huge hardware overhead has challenged their applications. Recently, several binary and ternary networks, in which the costly multiply-accumulate operations can be replaced by accumulations or even binary logic operations, make the on-chip training of DNNs quite promising. Therefore there is a pressing need to build an architecture that could subsume these networks under a unified framework that achieves both higher performance and less overhead. To this end, two fundamental issues are yet to be addressed. The first one is how to implement the back propagation when neuronal activations are discrete. The second one is how to remove the full-precision hidden weights in the training phase to break the bottlenecks of memory/computation consumption. To address the first issue, we present a multi-step neuronal activation discretization method and a derivative approximation technique that enable the implementing the back propagation algorithm on discrete DNNs. While for the second issue, we propose a discrete state transition (DST) methodology to constrain the weights in a discrete space without saving the hidden weights. Through this way, we build a unified framework that subsumes the binary or ternary networks as its special cases, and under which a heuristic algorithm is provided at the website https://github.com/AcrossV/Gated-XNOR. More particularly, we find that when both the weights and activations become ternary values, the DNNs can be reduced to sparse binary networks, termed as Gated XNOR networks (GXNOR-Nets) since only the event of non-zero weight and non-zero activation enables the Control Gate to start the XNOR logic operations in the original binary networks. This promises the event-driven hardware design for efficient mobile intelligence. We achieve advanced performance compared with state-of-the-art algorithms. Furthermore, the computational sparsity and the number of states in the discrete space can be flexibly modified to make it suitable for various hardware platforms.

  • gxnor net training deep neural networks with ternary weights and activations without full precision memory under a unified discretization framework
    arXiv: Learning, 2017
    Co-Authors: Lei Deng, Peng Jiao, Jing Pei
    Abstract:

    There is a pressing need to build an architecture that could subsume these networks under a unified framework that achieves both higher performance and less overhead. To this end, two fundamental issues are yet to be addressed. The first one is how to implement the back propagation when neuronal activations are discrete. The second one is how to remove the full-precision hidden weights in the training phase to break the bottlenecks of memory/computation consumption. To address the first issue, we present a multi-step neuronal activation discretization method and a derivative approximation technique that enable the implementing the back propagation algorithm on discrete DNNs. While for the second issue, we propose a discrete state transition (DST) methodology to constrain the weights in a discrete space without saving the hidden weights. Through this way, we build a unified framework that subsumes the binary or ternary networks as its special cases, and under which a heuristic algorithm is provided at the website this https URL. More particularly, we find that when both the weights and activations become ternary values, the DNNs can be reduced to sparse binary networks, termed as Gated XNOR networks (GXNOR-Nets) since only the event of non-zero weight and non-zero activation enables the Control Gate to start the XNOR logic operations in the original binary networks. This promises the event-driven hardware design for efficient mobile intelligence. We achieve advanced performance compared with state-of-the-art algorithms. Furthermore, the computational sparsity and the number of states in the discrete space can be flexibly modified to make it suitable for various hardware platforms.

Megumi Ishiduki - One of the best experts on this subject based on the ideXlab platform.

Jing Pei - One of the best experts on this subject based on the ideXlab platform.

  • gxnor net training deep neural networks with ternary weights and activations without full precision memory under a unified discretization framework
    Neural Networks, 2018
    Co-Authors: Lei Deng, Peng Jiao, Jing Pei
    Abstract:

    Although deep neural networks (DNNs) are being a revolutionary power to open up the AI era, the notoriously huge hardware overhead has challenged their applications. Recently, several binary and ternary networks, in which the costly multiply-accumulate operations can be replaced by accumulations or even binary logic operations, make the on-chip training of DNNs quite promising. Therefore there is a pressing need to build an architecture that could subsume these networks under a unified framework that achieves both higher performance and less overhead. To this end, two fundamental issues are yet to be addressed. The first one is how to implement the back propagation when neuronal activations are discrete. The second one is how to remove the full-precision hidden weights in the training phase to break the bottlenecks of memory/computation consumption. To address the first issue, we present a multi-step neuronal activation discretization method and a derivative approximation technique that enable the implementing the back propagation algorithm on discrete DNNs. While for the second issue, we propose a discrete state transition (DST) methodology to constrain the weights in a discrete space without saving the hidden weights. Through this way, we build a unified framework that subsumes the binary or ternary networks as its special cases, and under which a heuristic algorithm is provided at the website https://github.com/AcrossV/Gated-XNOR. More particularly, we find that when both the weights and activations become ternary values, the DNNs can be reduced to sparse binary networks, termed as Gated XNOR networks (GXNOR-Nets) since only the event of non-zero weight and non-zero activation enables the Control Gate to start the XNOR logic operations in the original binary networks. This promises the event-driven hardware design for efficient mobile intelligence. We achieve advanced performance compared with state-of-the-art algorithms. Furthermore, the computational sparsity and the number of states in the discrete space can be flexibly modified to make it suitable for various hardware platforms.

  • gxnor net training deep neural networks with ternary weights and activations without full precision memory under a unified discretization framework
    arXiv: Learning, 2017
    Co-Authors: Lei Deng, Peng Jiao, Jing Pei
    Abstract:

    There is a pressing need to build an architecture that could subsume these networks under a unified framework that achieves both higher performance and less overhead. To this end, two fundamental issues are yet to be addressed. The first one is how to implement the back propagation when neuronal activations are discrete. The second one is how to remove the full-precision hidden weights in the training phase to break the bottlenecks of memory/computation consumption. To address the first issue, we present a multi-step neuronal activation discretization method and a derivative approximation technique that enable the implementing the back propagation algorithm on discrete DNNs. While for the second issue, we propose a discrete state transition (DST) methodology to constrain the weights in a discrete space without saving the hidden weights. Through this way, we build a unified framework that subsumes the binary or ternary networks as its special cases, and under which a heuristic algorithm is provided at the website this https URL. More particularly, we find that when both the weights and activations become ternary values, the DNNs can be reduced to sparse binary networks, termed as Gated XNOR networks (GXNOR-Nets) since only the event of non-zero weight and non-zero activation enables the Control Gate to start the XNOR logic operations in the original binary networks. This promises the event-driven hardware design for efficient mobile intelligence. We achieve advanced performance compared with state-of-the-art algorithms. Furthermore, the computational sparsity and the number of states in the discrete space can be flexibly modified to make it suitable for various hardware platforms.

Takashi Maeda - One of the best experts on this subject based on the ideXlab platform.