The Experts below are selected from a list of 65838 Experts worldwide ranked by ideXlab platform

Douglas L. Jones - One of the best experts on this subject based on the ideXlab platform.

  • ISCAS - Variation-tolerant, low-power PN-code acquisition using stochastic sensor NOC
    2008 IEEE International Symposium on Circuits and Systems, 2008
    Co-Authors: G.v. Varatkar, Naresh R. Shanbhag, Sriram Narayanan, Douglas L. Jones
    Abstract:

    Presented in this paper is an energy-efficient and variation-tolerant PN-code acquisition Architecture for the wireless CDMA2000 standard. The Architectures is based on the recently proposed stochastic sensor network-on-chip (SSNOC) computational paradigm. The latter employs the principles of statistically similar decomposition and robust estimation theory to compensate for timing errors due to process variations. Performance of the SSNOC-based PN-code acquisition Architecture at the slow process corner indicates that the average probability of detection PDet improves by up to 3 orders-of-magnitude over that of the Conventional Architecture, while the variation in PDet(sigma / mu) is reduced by up to 2 orders-of-magnitude over that of the Conventional Architecture while simultaneously achieving a power reduction of 39%.

  • ACM Great Lakes Symposium on VLSI - Trends in energy-efficiency and robustness using stochastic sensor network-on-a-chip
    Proceedings of the 18th ACM Great Lakes symposium on VLSI - GLSVLSI '08, 2008
    Co-Authors: G.v. Varatkar, Naresh R. Shanbhag, Sriram Narayanan, Douglas L. Jones
    Abstract:

    The stochastic sensor network-on-chip (SSNOC) was recently proposed as an effective computational paradigm for jointly achieving energy-efficiency and robustness in nanoscale processes. In this paper, we study the trends in energy-efficiency and robustness exhibited by an SSNOC Architecture as the feature size scales from 130nm to 32nm for a PN-code acquisition application. The Conventional Architecture exhibits a 3 orders-of-magnitude loss in detection probability P_{det} due to process variations in the 130nm and smaller technology nodes. At the 130nm and 90nm nodes, the proposed SSNOC Architecture recovers from this performance loss, and exhibits a 2 orders-of-magnitude smaller variation in P_det compared to the Conventional Architecture. However, for the 65nm and 45nm technology nodes, the SSNOC Architecture with assistance from circuit level techniques such as adaptive body bias (ABB) and adaptive supply voltage (ASV) shows a 2-3 order-of-magnitude better detection performance. In addition, the SSNOC Architecture with ABB/ASV achieves 22% to 31% energy savings. For the 32nm node, the current version of SSNOC with ABB/ASV is not robust enough and thus motivates the need to explore even more powerful versions of SSNOC.

Chih-hung Yen - One of the best experts on this subject based on the ideXlab platform.

Zhangming Zhu - One of the best experts on this subject based on the ideXlab platform.

  • A novel split capacitor array switching scheme with proportional coefficient for SAR ADC
    Analog Integrated Circuits and Signal Processing, 2019
    Co-Authors: Ruixue Ding, Shaopeng Dong, Depeng Sun, Shubin Liu, Zhangming Zhu
    Abstract:

    A novel switching scheme with proportional coefficient for successive approximation register analog-to-digital converter is presented in this work. The proposed switching scheme realize proportional coefficient by means of charge-sharing, which can achieve a high energy efficiency. Due to the split capacitor array structure is adopted here, the total capacitance can be reduced by 96.9% over the Conventional structure. Moreover, the bridge capacitor is the unit capacitor, which is very convenient for layout design and capacitance matching. Furthermore, the proposed switching scheme reduces the energy by 99.9% compared with the Conventional Architecture through using the MSB-split switching structure and the single-side method. The proposed switching scheme also has a good performance in reset energy consumption and linearity. Based on the MATLAB simulation results, the maximum differential nonlinearity and maximum integral nonlinearity results of the proposed switching scheme are 0.626 LSB and 0.727 LSB, respectively.

  • Energy-efficient common-mode voltage switching scheme for SAR ADCs
    Analog Integrated Circuits and Signal Processing, 2016
    Co-Authors: Wei Guo, Zhangming Zhu
    Abstract:

    An energy-efficient switching scheme with common-mode voltage variation in 1LSB for successive approximation register analogue-to-digital converters is proposed. Based on the two-step Architecture, spilt-capacitor method and reusing of the unit capacitor technique, the proposed switching scheme achieves 99.35 % less switching energy and 73.4 % less number of capacitors over the Conventional Architecture with common-mode voltage variation in 1LSB.

  • High efficiency two-step capacitor switching scheme for SAR ADC
    Analog Integrated Circuits and Signal Processing, 2015
    Co-Authors: Zhen Ding, Zhangming Zhu
    Abstract:

    A high efficiency two-step capacitor switching scheme for a successive approximation register analogue-to-digital converter is presented. Two-step Architecture, split capacitor array, C-2C dummy capacitor and multiple switching schemes are combined in the proposed switching scheme. The proposed switching scheme achieves a 99.75 % reduction in switching energy and the total capacitance is reduced 85.9 % compared with the Conventional Architecture.

  • v cm based monotonic capacitor switching scheme for sar adc
    Electronics Letters, 2013
    Co-Authors: Zhangming Zhu, Yu Xiao, Xiaoli Song
    Abstract:

    A novel energy-efficient V CM -based monotonic capacitor switching scheme for successive approximation register (SAR) analogue to-digital converters (ADCs) is proposed. Based on the third reference voltage V CM and monotonic capacitor switching procedure, the proposed switching scheme achieves 97.66% less switching energy and 75% less number of capacitors over the Conventional Architecture, resulting in the most energy-efficient switching scheme among the reported switching sequences.

G.v. Varatkar - One of the best experts on this subject based on the ideXlab platform.

  • ACM Great Lakes Symposium on VLSI - Trends in energy-efficiency and robustness using stochastic sensor network-on-a-chip
    Proceedings of the 18th ACM Great Lakes symposium on VLSI - GLSVLSI '08, 2008
    Co-Authors: G.v. Varatkar, Naresh R. Shanbhag, Sriram Narayanan, Douglas L. Jones
    Abstract:

    The stochastic sensor network-on-chip (SSNOC) was recently proposed as an effective computational paradigm for jointly achieving energy-efficiency and robustness in nanoscale processes. In this paper, we study the trends in energy-efficiency and robustness exhibited by an SSNOC Architecture as the feature size scales from 130nm to 32nm for a PN-code acquisition application. The Conventional Architecture exhibits a 3 orders-of-magnitude loss in detection probability P_{det} due to process variations in the 130nm and smaller technology nodes. At the 130nm and 90nm nodes, the proposed SSNOC Architecture recovers from this performance loss, and exhibits a 2 orders-of-magnitude smaller variation in P_det compared to the Conventional Architecture. However, for the 65nm and 45nm technology nodes, the SSNOC Architecture with assistance from circuit level techniques such as adaptive body bias (ABB) and adaptive supply voltage (ASV) shows a 2-3 order-of-magnitude better detection performance. In addition, the SSNOC Architecture with ABB/ASV achieves 22% to 31% energy savings. For the 32nm node, the current version of SSNOC with ABB/ASV is not robust enough and thus motivates the need to explore even more powerful versions of SSNOC.

  • ISCAS - Variation-tolerant, low-power PN-code acquisition using stochastic sensor NOC
    2008 IEEE International Symposium on Circuits and Systems, 2008
    Co-Authors: G.v. Varatkar, Naresh R. Shanbhag, Sriram Narayanan, Douglas L. Jones
    Abstract:

    Presented in this paper is an energy-efficient and variation-tolerant PN-code acquisition Architecture for the wireless CDMA2000 standard. The Architectures is based on the recently proposed stochastic sensor network-on-chip (SSNOC) computational paradigm. The latter employs the principles of statistically similar decomposition and robust estimation theory to compensate for timing errors due to process variations. Performance of the SSNOC-based PN-code acquisition Architecture at the slow process corner indicates that the average probability of detection PDet improves by up to 3 orders-of-magnitude over that of the Conventional Architecture, while the variation in PDet(sigma / mu) is reduced by up to 2 orders-of-magnitude over that of the Conventional Architecture while simultaneously achieving a power reduction of 39%.

  • SiPS - Variation-Tolerant Motion Estimation Architecture
    2007 IEEE Workshop on Signal Processing Systems, 2007
    Co-Authors: G.v. Varatkar, Naresh R. Shanbhag
    Abstract:

    In this paper, we study the trade-off between energy-efficiency and variation-tolerance of an error-resilient motion estimation Architecture. Error-resiliency is incorporated via algorithmic noise-tolerance (ANT) where an input subsampled replica (ISR) of the main sum-of-absolute-difference(MSAD) block is employed for detecting and correcting errors in the MSAD block. This Architecture is referred to as ISR-ANT. In the presence of process variations, the average peak signal-to-noise ratio (PSNR) of ISR-ANT Architecture increases by up to 1.8dB over that of the Conventional Architecture in 130nm IBM process technology. Furthermore, the PSNR variation is also reduced by 7× over that of the Conventional Architecture at the slow corner while achieving a power reduction of 33%.

Qiang Li - One of the best experts on this subject based on the ideXlab platform.

  • Coverage and Handover Analysis of Ultra-Dense Millimeter-Wave Networks With Control and User Plane Separation Architecture
    IEEE Access, 2018
    Co-Authors: Bin Yang, Xuan Yang, Xiaohu Ge, Qiang Li
    Abstract:

    The control and user plane separation (CUPS) Architecture becomes more appealing for higher mobility profiles with the densification of networks. Compared with the Conventional Architecture where the control plane and the user plane are closely coupled, CUPS Architecture is envisioned to provide enhancement for networks in a flexible way, e.g., reducing latency on application service, while not affecting the functionality of the existing base stations (BSs). In this paper, we compare the performance of ultra-dense millimeter-wave networks with the CUPS Architecture and the Conventional Architecture. An analytical framework is proposed to study the coverage probability, which takes the propagation characteristic of millimeter wave into consideration. The proposed framework is then simplified in an ultra-dense scenario, where two optimization problems are formulated to achieve the minimum handover cost subject to a certain coverage probability requirement. Numerical results show that the CUPS Architecture outperforms the Conventional Architecture in terms of the coverage probability as well as the handover cost. Moreover, new insights are obtained on the deployment of ultra-dense millimeter-wave networks. To be specific, the handover cost of networks with the Conventional Architecture can be effectively reduced by adding more macrocell BSs, while it is beneficial to add smaller cell BSs into networks with the CUPS Architecture.

  • Improved Radio Frequency Receiver Front-end for Magnetic Resonance Imaging
    Conference proceedings : ... Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and, 2005
    Co-Authors: Xueqin Jia, Qiang Li, Xu Wang, Jinghong Li
    Abstract:

    Based on software radio theory, this paper focuses on researching a direct conversion structure for the radio frequency (RF) receiver front-end and tries to apply this flexible receiver front-end in MRI receiving system. In particular, we look at the Conventional Architecture of RF receiver front-ends of MRI; present Architecture of a direct conversion for RF receiver front-end of MRI; outline the key aspects of designing such multi-channel and multi-mode front-end systems. In addition, based on this Architecture, a practical RF front-end receiving system of MRI is given. Two parts are included in this system; one is the Conventional receiver front-end the other is the direct conversion design for RF receiver front-end of MRI