The Experts below are selected from a list of 81 Experts worldwide ranked by ideXlab platform

Colm J. Prendergast - One of the best experts on this subject based on the ideXlab platform.

  • A PAL/NTSC Digital Video Encoder on 0.6-/spl mu/m CMOS with 66 dB typical SNR, 0.4% differential gain, and 0.2/spl deg/ differential phase
    IEEE Journal of Solid-state Circuits, 1997
    Co-Authors: Timothy J. Cummins, Brian P. Murray, Colm J. Prendergast
    Abstract:

    A Digital Video Encoder chip which generates phase alternate (PAL) or National Television Standards Committee (NTSC) analog Video output signals is presented. The chip operates from 3 to 5.5 V; typical differential gain and phase performance at 5 V is 0.4% and 0.2/spl deg/, respectively, and SNR is 66 dB rms. The architecture, circuit, and die size minimization techniques used to achieve this performance in a 4/spl times/4 mm CMOS die are presented. The die is packaged in a 44-pin plastic quad flatpack package (7/spl times/7 mm). The Digital logic has 47 k gates and achieves an average power dissipation of 0.37 /spl mu/W/gate/MHz. The paper also covers the circuit and packaging techniques used to reduce power, /spl Theta/ J-A, and junction temperature in this package in order to allow continuous operation in still-air ambient temperatures of 70/spl deg/C.

  • a pal ntsc Digital Video Encoder on 0 6 spl mu m cmos with 66 db typical snr 0 4 differential gain and 0 2 spl deg differential phase
    IEEE Journal of Solid-state Circuits, 1997
    Co-Authors: Timothy J. Cummins, Brian P. Murray, Colm J. Prendergast
    Abstract:

    A Digital Video Encoder chip which generates phase alternate (PAL) or National Television Standards Committee (NTSC) analog Video output signals is presented. The chip operates from 3 to 5.5 V; typical differential gain and phase performance at 5 V is 0.4% and 0.2/spl deg/, respectively, and SNR is 66 dB rms. The architecture, circuit, and die size minimization techniques used to achieve this performance in a 4/spl times/4 mm CMOS die are presented. The die is packaged in a 44-pin plastic quad flatpack package (7/spl times/7 mm). The Digital logic has 47 k gates and achieves an average power dissipation of 0.37 /spl mu/W/gate/MHz. The paper also covers the circuit and packaging techniques used to reduce power, /spl Theta/ J-A, and junction temperature in this package in order to allow continuous operation in still-air ambient temperatures of 70/spl deg/C.

Seungho Oh - One of the best experts on this subject based on the ideXlab platform.

  • design and implementation of a pipelined Digital Video ntsc pal pal plus Encoder
    Journal of electrical engineering and information science, 1999
    Co-Authors: Seungho Oh, Bongsoon Kang
    Abstract:

    This paper describes a design of a pipelined Digital Video Encoder using 4:3 decimation algorithm. By focusing on multiplier-free structures, the structure of the Video Encoder is optimized. The proposed Video Encoder processes conventional NTSC/PAL and PAL-plus Video signals using an improved decimation algorithm[5]. In order to support multistandard Video signals, a programmable pipelined archirecture is adopted to design various Digital filters. Interpolation filters are also used to enhance SNR of encoded Video signals. The proposed Encoder requires only 25K gates, which is a 41 % reduction in hardware compared with the systolic pipelined architecture in [5]. The Encoder has been designed in a 5-stage pipelined structure to assure stable operation. The overall performance of the Encoder has been verified by using 0.65um CMOS gatearray technology. The chip size is 5170um × 4350um and the power dissipation is 0.9W at 5V.

  • an asic implementation of an optimized Digital Video Encoder
    International Conference on Consumer Electronics, 1998
    Co-Authors: Seungho Oh, Bongsoon Kang
    Abstract:

    This paper presents a design of an optimized Video Encoder using a simple pipelined architecture. The proposed Video Encoder accepts conventional NTSC/PAL Video signals. It also processes the PALplus Video signal using an improved decimation process. The proposed Encoder requires only 25 K gates, which is a 41% reduction in hardware compared with the systolic pipelined architecture of Oh, Choi, Kwon and Lee (see ibid., vol.43, no.3, p.965-71, 1997). The Encoder has been designed in a 5-stage pipelined structure to assure stable operation. The overall performance of the Encoder has been verified by using 0.65 /spl mu/m CMOS gate array technology. The chip size is 5170 /spl mu/m * 435O /spl mu/m.

  • a design of a multistandard Digital Video Encoder using a pipelined architecture
    Journal of electrical engineering and information science, 1997
    Co-Authors: Seungho Oh, Hanjun Choi, Sungwoo Kwon
    Abstract:

    This paper describes the design of a multistandard Video Encoder. The proposed Encoder accepts conventional NTSC/PAL Video signals. It also processes the PAL-plus Video signal which is now popular in Europe. The Encoder consists of five major building functions which are letter-box convener, color space converter, Digital filters, color modulator, and timing generator. In order to support multistandard Video signals, a programmable systolic architecture is adopted in designing various Digital filters. Interpolation Digital filters are also used to enhance signal-to-noise ratio of encoded Video signals. The input to the Encoder can be either YCbCr signal or RGB signal. The outputs are luminance(Y), chrominance(C), and composite Video baseband(Y+C) signals. The architecture of the Encoder is defined by using Matlab program and is modelled by using Verilog-HDL language. The overall operation is verified by using various Video signals, such as color bar patterns, ramp signals, and so on The Encoder contains 42K gates and is implemented by using 0.6um CMOS process.

  • a fully programmable systolic pipelined Digital Video Encoder for ntsc pal palplus compatibility on a 4 3 screen
    International Conference on Consumer Electronics, 1997
    Co-Authors: Sungwoo Kwon, Hanjun Choi, Seungho Oh
    Abstract:

    An Encoder is proposed that supports NTSC and PAL systems. In addition, it also permits the PALplus standard mode, that is compatible to a 16:9 wide screen, on a 4:3 screen. In order for this to be realized the vertical and horizontal synchronous timing are fully programmable and the Encoder is designed in a systolic pipelined architecture with a double pixel clock to increase the internal processing speed. Also, we have mainly concentrated on reducing the gate counts of the submodules such as the letter-box converter, color converter matrix, low pass filter, interpolator, and color modulator. The Encoder can accept RGB and YCbCr as the input pixel signal with a speed of 10-15 Mpps. The outputs are a Y/C (S-Video) signal and a composite signal. We have modeled the Encoder in Verilog-HDL and verified its overall operation by feeding the top module with a color bar test signal. The Encoder, which was implemented by 0.6 /spl mu/m CMOS technology, contains about 42 k gates.

  • A Fully Programmable Systolic Pipelined Digital Video Encoder For NTSC/PAL/PALplus Compatibility On A 4:3 Screen
    IEEE Transactions on Consumer Electronics, 1997
    Co-Authors: Sungwoo Kwon, Hanjun Choi, Seungho Oh
    Abstract:

    An Encoder is proposed that supports NTSC and PAL systems. In addition, it also permits the PALplus standard mode, that is compatible to a 16:9 wide screen, on a 4:3 screen. In order for this to be realized the vertical and horizontal synchronous timing are fully programmable and the Encoder is designed in a systolic pipelined architecture with a double pixel clock to increase the internal processing speed. Also, we have mainly concentrated on reducing the gate counts of the submodules such as the letter-box converter, color converter matrix, low pass filter, interpolator, and color modulator. The Encoder can accept RGB and YCbCr as the input pixel signal with a speed of 10-15 Mpps. The outputs are a Y/C (S-Video) signal and a composite signal. We have modeled the Encoder in Verilog-HDL and verified its overall operation by feeding the top module with a color bar test signal. The Encoder, which was implemented by 0.6 /spl mu/m CMOS technology, contains about 42 k gates.

Timothy J. Cummins - One of the best experts on this subject based on the ideXlab platform.

  • A PAL/NTSC Digital Video Encoder on 0.6-/spl mu/m CMOS with 66 dB typical SNR, 0.4% differential gain, and 0.2/spl deg/ differential phase
    IEEE Journal of Solid-state Circuits, 1997
    Co-Authors: Timothy J. Cummins, Brian P. Murray, Colm J. Prendergast
    Abstract:

    A Digital Video Encoder chip which generates phase alternate (PAL) or National Television Standards Committee (NTSC) analog Video output signals is presented. The chip operates from 3 to 5.5 V; typical differential gain and phase performance at 5 V is 0.4% and 0.2/spl deg/, respectively, and SNR is 66 dB rms. The architecture, circuit, and die size minimization techniques used to achieve this performance in a 4/spl times/4 mm CMOS die are presented. The die is packaged in a 44-pin plastic quad flatpack package (7/spl times/7 mm). The Digital logic has 47 k gates and achieves an average power dissipation of 0.37 /spl mu/W/gate/MHz. The paper also covers the circuit and packaging techniques used to reduce power, /spl Theta/ J-A, and junction temperature in this package in order to allow continuous operation in still-air ambient temperatures of 70/spl deg/C.

  • a pal ntsc Digital Video Encoder on 0 6 spl mu m cmos with 66 db typical snr 0 4 differential gain and 0 2 spl deg differential phase
    IEEE Journal of Solid-state Circuits, 1997
    Co-Authors: Timothy J. Cummins, Brian P. Murray, Colm J. Prendergast
    Abstract:

    A Digital Video Encoder chip which generates phase alternate (PAL) or National Television Standards Committee (NTSC) analog Video output signals is presented. The chip operates from 3 to 5.5 V; typical differential gain and phase performance at 5 V is 0.4% and 0.2/spl deg/, respectively, and SNR is 66 dB rms. The architecture, circuit, and die size minimization techniques used to achieve this performance in a 4/spl times/4 mm CMOS die are presented. The die is packaged in a 44-pin plastic quad flatpack package (7/spl times/7 mm). The Digital logic has 47 k gates and achieves an average power dissipation of 0.37 /spl mu/W/gate/MHz. The paper also covers the circuit and packaging techniques used to reduce power, /spl Theta/ J-A, and junction temperature in this package in order to allow continuous operation in still-air ambient temperatures of 70/spl deg/C.

Brian P. Murray - One of the best experts on this subject based on the ideXlab platform.

  • A PAL/NTSC Digital Video Encoder on 0.6-/spl mu/m CMOS with 66 dB typical SNR, 0.4% differential gain, and 0.2/spl deg/ differential phase
    IEEE Journal of Solid-state Circuits, 1997
    Co-Authors: Timothy J. Cummins, Brian P. Murray, Colm J. Prendergast
    Abstract:

    A Digital Video Encoder chip which generates phase alternate (PAL) or National Television Standards Committee (NTSC) analog Video output signals is presented. The chip operates from 3 to 5.5 V; typical differential gain and phase performance at 5 V is 0.4% and 0.2/spl deg/, respectively, and SNR is 66 dB rms. The architecture, circuit, and die size minimization techniques used to achieve this performance in a 4/spl times/4 mm CMOS die are presented. The die is packaged in a 44-pin plastic quad flatpack package (7/spl times/7 mm). The Digital logic has 47 k gates and achieves an average power dissipation of 0.37 /spl mu/W/gate/MHz. The paper also covers the circuit and packaging techniques used to reduce power, /spl Theta/ J-A, and junction temperature in this package in order to allow continuous operation in still-air ambient temperatures of 70/spl deg/C.

  • a pal ntsc Digital Video Encoder on 0 6 spl mu m cmos with 66 db typical snr 0 4 differential gain and 0 2 spl deg differential phase
    IEEE Journal of Solid-state Circuits, 1997
    Co-Authors: Timothy J. Cummins, Brian P. Murray, Colm J. Prendergast
    Abstract:

    A Digital Video Encoder chip which generates phase alternate (PAL) or National Television Standards Committee (NTSC) analog Video output signals is presented. The chip operates from 3 to 5.5 V; typical differential gain and phase performance at 5 V is 0.4% and 0.2/spl deg/, respectively, and SNR is 66 dB rms. The architecture, circuit, and die size minimization techniques used to achieve this performance in a 4/spl times/4 mm CMOS die are presented. The die is packaged in a 44-pin plastic quad flatpack package (7/spl times/7 mm). The Digital logic has 47 k gates and achieves an average power dissipation of 0.37 /spl mu/W/gate/MHz. The paper also covers the circuit and packaging techniques used to reduce power, /spl Theta/ J-A, and junction temperature in this package in order to allow continuous operation in still-air ambient temperatures of 70/spl deg/C.

Sungwoo Kwon - One of the best experts on this subject based on the ideXlab platform.

  • a design of a multistandard Digital Video Encoder using a pipelined architecture
    Journal of electrical engineering and information science, 1997
    Co-Authors: Seungho Oh, Hanjun Choi, Sungwoo Kwon
    Abstract:

    This paper describes the design of a multistandard Video Encoder. The proposed Encoder accepts conventional NTSC/PAL Video signals. It also processes the PAL-plus Video signal which is now popular in Europe. The Encoder consists of five major building functions which are letter-box convener, color space converter, Digital filters, color modulator, and timing generator. In order to support multistandard Video signals, a programmable systolic architecture is adopted in designing various Digital filters. Interpolation Digital filters are also used to enhance signal-to-noise ratio of encoded Video signals. The input to the Encoder can be either YCbCr signal or RGB signal. The outputs are luminance(Y), chrominance(C), and composite Video baseband(Y+C) signals. The architecture of the Encoder is defined by using Matlab program and is modelled by using Verilog-HDL language. The overall operation is verified by using various Video signals, such as color bar patterns, ramp signals, and so on The Encoder contains 42K gates and is implemented by using 0.6um CMOS process.

  • a fully programmable systolic pipelined Digital Video Encoder for ntsc pal palplus compatibility on a 4 3 screen
    International Conference on Consumer Electronics, 1997
    Co-Authors: Sungwoo Kwon, Hanjun Choi, Seungho Oh
    Abstract:

    An Encoder is proposed that supports NTSC and PAL systems. In addition, it also permits the PALplus standard mode, that is compatible to a 16:9 wide screen, on a 4:3 screen. In order for this to be realized the vertical and horizontal synchronous timing are fully programmable and the Encoder is designed in a systolic pipelined architecture with a double pixel clock to increase the internal processing speed. Also, we have mainly concentrated on reducing the gate counts of the submodules such as the letter-box converter, color converter matrix, low pass filter, interpolator, and color modulator. The Encoder can accept RGB and YCbCr as the input pixel signal with a speed of 10-15 Mpps. The outputs are a Y/C (S-Video) signal and a composite signal. We have modeled the Encoder in Verilog-HDL and verified its overall operation by feeding the top module with a color bar test signal. The Encoder, which was implemented by 0.6 /spl mu/m CMOS technology, contains about 42 k gates.

  • A Fully Programmable Systolic Pipelined Digital Video Encoder For NTSC/PAL/PALplus Compatibility On A 4:3 Screen
    IEEE Transactions on Consumer Electronics, 1997
    Co-Authors: Sungwoo Kwon, Hanjun Choi, Seungho Oh
    Abstract:

    An Encoder is proposed that supports NTSC and PAL systems. In addition, it also permits the PALplus standard mode, that is compatible to a 16:9 wide screen, on a 4:3 screen. In order for this to be realized the vertical and horizontal synchronous timing are fully programmable and the Encoder is designed in a systolic pipelined architecture with a double pixel clock to increase the internal processing speed. Also, we have mainly concentrated on reducing the gate counts of the submodules such as the letter-box converter, color converter matrix, low pass filter, interpolator, and color modulator. The Encoder can accept RGB and YCbCr as the input pixel signal with a speed of 10-15 Mpps. The outputs are a Y/C (S-Video) signal and a composite signal. We have modeled the Encoder in Verilog-HDL and verified its overall operation by feeding the top module with a color bar test signal. The Encoder, which was implemented by 0.6 /spl mu/m CMOS technology, contains about 42 k gates.