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M S Shur - One of the best experts on this subject based on the ideXlab platform.
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the extrinsic compact model of the mosfet Drain current based on a new interpolation expression for the transition between linear and saturation regimes with a monotonic decrease of the differential conductance to a nonzero value
IEEE Electron Devices Technology and Manufacturing Conference, 2020Co-Authors: Valentin O Turin, G I Zebrev, Roman Shkarlat, B Iniguez, M S ShurAbstract:Previously, we proposed a new interpolation expression to bridge the transition between the linear and the saturation regimes of “intrinsic” MOSFET. This approach, in contrast to the traditional one, gives a monotonic decrease of the differential conductance from the maximum value in the linear regime to the minimum value in the saturation regime. Later, we proposed a linear approximation for an “extrinsic” MOSFET Drain current dependence on the “extrinsic” Drain Bias in the saturation regime for not very high Drain Bias when nonlinear effects can be neglected. To obtain this approximation, an equation for the output differential resistance of the “extrinsic” MOSFET in saturation regime was obtained, that is similar to the result known from the theory of the common source MOSFET amplifier with source degeneration. In this paper, we combine these two results and present an “extrinsic” compact model for a short-channel MOSFET above threshold Drain current with proper account of the differential conductance in the saturation regime.
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a linear extrinsic compact model for short channel mosfet Drain current asymptotic dependence on Drain Bias in saturation regime
International Conference on Micro- and Nano-Electronics 2018, 2019Co-Authors: Valentin O Turin, G I Zebrev, Roman Shkarlat, V Poyarkov, O Kshensky, B Iniguez, M S ShurAbstract:We derived the equation for the Drain current of a short-channel MOSFET with nonzero differential conductance in saturation regime describing its nonlinear dependence on “extrinsic” Drain Bias and accounting for the parasitic and contact series resistances. This implicit equation could be numerically solved in the entire range of the Drain Biases. We have also derived the equation for the differential conductance of the “extrinsic” MOSFET in the saturation regime. Finally, we have proposed a linear approximation for asymptotic dependence of the “extrinsic” MOSFET Drain current on “extrinsic” Drain Bias in saturation regime.
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terahertz response of field effect transistors in saturation regime
Applied Physics Letters, 2011Co-Authors: T A Elkhatib, Yu V Kachorovskii, W Stillman, S L Rumyantsev, X C Zhang, M S ShurAbstract:We report on the broadband terahertz response of InGaAs/GaAs high electron mobility transistors operating at 1.63 THz and room temperature deep in the saturation regime. We demonstrate that responses show linear increase with Drain-to-source voltage (or Drain-Bias current) and might reach very high values up to 170 V/W. We also develop a phenomenological theory valid both in the Ohmic and in the saturation regimes.
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terahertz response of field effect transistors in saturation regime
arXiv: Instrumentation and Detectors, 2010Co-Authors: T A Elkhatib, Yu V Kachorovskii, W Stillman, S L Rumyantsev, X C Zhang, M S ShurAbstract:We report on the broadband THz response of InGaAs/GaAs HEMTs operating at 1.63 THz and room temperature deep in the saturation regime. We demonstrate that responses show linear increase with Drain-to-source voltage (or Drain Bias current) and reach very high values up to 170V/W. We also develop a phenomenological theory valid both in the ohmic and in the saturation regimes.
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contact resistance extraction in pentacene thin film transistors
Solid-state Electronics, 2003Co-Authors: Peter V Necliudov, M S Shur, David J Gundlach, T N JacksonAbstract:Abstract We report on the contact resistances for pentacene thin film transistors with two different designs: top and bottom contact configurations (referred to as TC and BC TFTs, respectively) for two different contact metals (gold and palladium). The extraction was done based on the dependencies of the channel resistances on the gate length and gate voltage. The extracted gold TC TFT contact resistance depends on VGS, but shows no dependence on the Drain Bias. The TC TFT contact resistance is comparable to or exceeds the channel resistance for channels shorter than approximately 10 μm. The contact resistance of BC TFTs depends both on gate and Drain Bias. We propose a circuit simulating the BC TFT contact resistance and verify the circuit applicability by extracting and comparing the TFT channel resistances at different Drain voltages. Our results reveal an important role played by contact resistances and provide an accurate model of the contact phenomena suitable for implementation in Spice or other circuit simulators.
Jongin Kim - One of the best experts on this subject based on the ideXlab platform.
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local degradation induced threshold voltage shift in turned off amorphous ingazno thin film transistors under ac Drain Bias stress
IEEE Electron Device Letters, 2015Co-Authors: Jongin Kim, Intak Cho, Chanyong Jeong, Daeun Lee, Hyuckin Kwon, Keum Dong Jung, Mun Soo Park, Mi Seon Seo, Tae Young Kim, Jehun LeeAbstract:Local degradation caused by Drain Bias ( $V_{\mathrm {\mathbf {DS}}}$ ) stressing is recently considered as a key issue in amorphous InGaZnO (a-IGZO) thin film transistors (TFTs). In this letter, we investigate the instability of turned-OFF a-IGZO TFTs under ac $V_{\mathrm {\mathbf {DS}}}$ stressing. The negative threshold voltage shift, which was well fitted by a stretched exponential function, was accelerated with increasing duty cycle despite the same effective stress time. A capacitance measurement reveals that a higher duty cycle induced more donor states near the Drain, implying that the stretched-exponential time dependence cannot be fully explained by trapping mechanism. Temperature-dependent $\tau $ followed the Arrhenius relation, whereas $\beta $ showed unusual temperature dependence in contrast to that under dc $V_{\mathrm {\mathbf {DS}}}$ stressing. These findings suggest an additional origin such as a stress release effect under an ac $V_{\mathrm {\mathbf {DS}}}$ stress other than hopping/tunneling mechanism.
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effect of temperature and electric field on degradation in amorphous ingazno tfts under positive gate and Drain Bias stress
IEEE Electron Device Letters, 2014Co-Authors: Jongin Kim, Intak Cho, Chanyong Jeong, Daeun Lee, Hyuckin Kwon, Sungmin Joe, Sung Hun Jin, Jongho LeeAbstract:The mechanism of the electrical degradation in amorphous InGaZnO thin-film transistors under a positive gate and Drain Bias stress is investigated. The stress tests under various combinations of Bias and temperature reveal that the negative shift of transfer curves accompanied by a hump is attributed to not an electric field or heating alone, but the simultaneous effect of them. Furthermore, the mitigated degradation under a pulsed stress of a reduced pulse period from 2 s to 0.1 ms and the difference in output characteristics between a dc sweep and a pulsed sweep measurements imply that self-heating with the high field could be the main cause of the degradation rather than hot-carrier effect.
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a study on the degradation mechanism of ingazno thin film transistors under simultaneous gate and Drain Bias stresses based on the electronic trap characterization
Semiconductor Science and Technology, 2014Co-Authors: Chanyong Jeong, Jongin Kim, Daeun Lee, Sanghun Song, Jongho Lee, Hyuckin KwonAbstract:We discuss the device degradation mechanism of amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistors (TFTs) under simultaneous gate and Drain Bias stresses based on the electronic trap characterization results. The transfer curve exhibits an apparent negative shift as the stress time increases, and a formation of hump is observed in the transfer curve after stresses. A notable increase of the frequency dispersion is observed after stresses in both gate-to-Drain capacitance–voltage (CGD–VG) and gate-to-source capacitance–voltage (CGS–VG) curves, which implies that the subgap states are generated by simultaneous gate and Drain Bias stresses, and the damaged location is not limited to the Drain side of TFTs. The larger frequency dispersion is observed in CGD–VG curves after stresses in a wider channel device, which implies that the heat is an important factor in the generation of the subgap states under simultaneous gate and Drain Bias stresses in a-IGZO TFTs. Based on the electronic trap characterization results, we conclude that the impact ionization near the Drain side of the device is not a dominant mechanism causing the generation of subgap states and device degradation in a-IGZO TFTs under simultaneous gate and Drain Bias stresses. The generation of oxygen vacancy-related donor-like traps near the conduction band edge is considered as a possible mechanism causing the device degradation under simultaneous gate and Drain Bias stresses in a-IGZO TFTs.
Hyuckin Kwon - One of the best experts on this subject based on the ideXlab platform.
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local degradation induced threshold voltage shift in turned off amorphous ingazno thin film transistors under ac Drain Bias stress
IEEE Electron Device Letters, 2015Co-Authors: Jongin Kim, Intak Cho, Chanyong Jeong, Daeun Lee, Hyuckin Kwon, Keum Dong Jung, Mun Soo Park, Mi Seon Seo, Tae Young Kim, Jehun LeeAbstract:Local degradation caused by Drain Bias ( $V_{\mathrm {\mathbf {DS}}}$ ) stressing is recently considered as a key issue in amorphous InGaZnO (a-IGZO) thin film transistors (TFTs). In this letter, we investigate the instability of turned-OFF a-IGZO TFTs under ac $V_{\mathrm {\mathbf {DS}}}$ stressing. The negative threshold voltage shift, which was well fitted by a stretched exponential function, was accelerated with increasing duty cycle despite the same effective stress time. A capacitance measurement reveals that a higher duty cycle induced more donor states near the Drain, implying that the stretched-exponential time dependence cannot be fully explained by trapping mechanism. Temperature-dependent $\tau $ followed the Arrhenius relation, whereas $\beta $ showed unusual temperature dependence in contrast to that under dc $V_{\mathrm {\mathbf {DS}}}$ stressing. These findings suggest an additional origin such as a stress release effect under an ac $V_{\mathrm {\mathbf {DS}}}$ stress other than hopping/tunneling mechanism.
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effect of temperature and electric field on degradation in amorphous ingazno tfts under positive gate and Drain Bias stress
IEEE Electron Device Letters, 2014Co-Authors: Jongin Kim, Intak Cho, Chanyong Jeong, Daeun Lee, Hyuckin Kwon, Sungmin Joe, Sung Hun Jin, Jongho LeeAbstract:The mechanism of the electrical degradation in amorphous InGaZnO thin-film transistors under a positive gate and Drain Bias stress is investigated. The stress tests under various combinations of Bias and temperature reveal that the negative shift of transfer curves accompanied by a hump is attributed to not an electric field or heating alone, but the simultaneous effect of them. Furthermore, the mitigated degradation under a pulsed stress of a reduced pulse period from 2 s to 0.1 ms and the difference in output characteristics between a dc sweep and a pulsed sweep measurements imply that self-heating with the high field could be the main cause of the degradation rather than hot-carrier effect.
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a study on the degradation mechanism of ingazno thin film transistors under simultaneous gate and Drain Bias stresses based on the electronic trap characterization
Semiconductor Science and Technology, 2014Co-Authors: Chanyong Jeong, Jongin Kim, Daeun Lee, Sanghun Song, Jongho Lee, Hyuckin KwonAbstract:We discuss the device degradation mechanism of amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistors (TFTs) under simultaneous gate and Drain Bias stresses based on the electronic trap characterization results. The transfer curve exhibits an apparent negative shift as the stress time increases, and a formation of hump is observed in the transfer curve after stresses. A notable increase of the frequency dispersion is observed after stresses in both gate-to-Drain capacitance–voltage (CGD–VG) and gate-to-source capacitance–voltage (CGS–VG) curves, which implies that the subgap states are generated by simultaneous gate and Drain Bias stresses, and the damaged location is not limited to the Drain side of TFTs. The larger frequency dispersion is observed in CGD–VG curves after stresses in a wider channel device, which implies that the heat is an important factor in the generation of the subgap states under simultaneous gate and Drain Bias stresses in a-IGZO TFTs. Based on the electronic trap characterization results, we conclude that the impact ionization near the Drain side of the device is not a dominant mechanism causing the generation of subgap states and device degradation in a-IGZO TFTs under simultaneous gate and Drain Bias stresses. The generation of oxygen vacancy-related donor-like traps near the conduction band edge is considered as a possible mechanism causing the device degradation under simultaneous gate and Drain Bias stresses in a-IGZO TFTs.
Chanyong Jeong - One of the best experts on this subject based on the ideXlab platform.
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local degradation induced threshold voltage shift in turned off amorphous ingazno thin film transistors under ac Drain Bias stress
IEEE Electron Device Letters, 2015Co-Authors: Jongin Kim, Intak Cho, Chanyong Jeong, Daeun Lee, Hyuckin Kwon, Keum Dong Jung, Mun Soo Park, Mi Seon Seo, Tae Young Kim, Jehun LeeAbstract:Local degradation caused by Drain Bias ( $V_{\mathrm {\mathbf {DS}}}$ ) stressing is recently considered as a key issue in amorphous InGaZnO (a-IGZO) thin film transistors (TFTs). In this letter, we investigate the instability of turned-OFF a-IGZO TFTs under ac $V_{\mathrm {\mathbf {DS}}}$ stressing. The negative threshold voltage shift, which was well fitted by a stretched exponential function, was accelerated with increasing duty cycle despite the same effective stress time. A capacitance measurement reveals that a higher duty cycle induced more donor states near the Drain, implying that the stretched-exponential time dependence cannot be fully explained by trapping mechanism. Temperature-dependent $\tau $ followed the Arrhenius relation, whereas $\beta $ showed unusual temperature dependence in contrast to that under dc $V_{\mathrm {\mathbf {DS}}}$ stressing. These findings suggest an additional origin such as a stress release effect under an ac $V_{\mathrm {\mathbf {DS}}}$ stress other than hopping/tunneling mechanism.
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effect of temperature and electric field on degradation in amorphous ingazno tfts under positive gate and Drain Bias stress
IEEE Electron Device Letters, 2014Co-Authors: Jongin Kim, Intak Cho, Chanyong Jeong, Daeun Lee, Hyuckin Kwon, Sungmin Joe, Sung Hun Jin, Jongho LeeAbstract:The mechanism of the electrical degradation in amorphous InGaZnO thin-film transistors under a positive gate and Drain Bias stress is investigated. The stress tests under various combinations of Bias and temperature reveal that the negative shift of transfer curves accompanied by a hump is attributed to not an electric field or heating alone, but the simultaneous effect of them. Furthermore, the mitigated degradation under a pulsed stress of a reduced pulse period from 2 s to 0.1 ms and the difference in output characteristics between a dc sweep and a pulsed sweep measurements imply that self-heating with the high field could be the main cause of the degradation rather than hot-carrier effect.
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a study on the degradation mechanism of ingazno thin film transistors under simultaneous gate and Drain Bias stresses based on the electronic trap characterization
Semiconductor Science and Technology, 2014Co-Authors: Chanyong Jeong, Jongin Kim, Daeun Lee, Sanghun Song, Jongho Lee, Hyuckin KwonAbstract:We discuss the device degradation mechanism of amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistors (TFTs) under simultaneous gate and Drain Bias stresses based on the electronic trap characterization results. The transfer curve exhibits an apparent negative shift as the stress time increases, and a formation of hump is observed in the transfer curve after stresses. A notable increase of the frequency dispersion is observed after stresses in both gate-to-Drain capacitance–voltage (CGD–VG) and gate-to-source capacitance–voltage (CGS–VG) curves, which implies that the subgap states are generated by simultaneous gate and Drain Bias stresses, and the damaged location is not limited to the Drain side of TFTs. The larger frequency dispersion is observed in CGD–VG curves after stresses in a wider channel device, which implies that the heat is an important factor in the generation of the subgap states under simultaneous gate and Drain Bias stresses in a-IGZO TFTs. Based on the electronic trap characterization results, we conclude that the impact ionization near the Drain side of the device is not a dominant mechanism causing the generation of subgap states and device degradation in a-IGZO TFTs under simultaneous gate and Drain Bias stresses. The generation of oxygen vacancy-related donor-like traps near the conduction band edge is considered as a possible mechanism causing the device degradation under simultaneous gate and Drain Bias stresses in a-IGZO TFTs.
Arindam Ghosh - One of the best experts on this subject based on the ideXlab platform.
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observation of trap assisted space charge limited conductivity in short channel mos2 transistor
Applied Physics Letters, 2013Co-Authors: Subhamoy Ghatak, Arindam GhoshAbstract:We present temperature dependent I-V measurements of short channel MoS2 field effect devices at high source-Drain Bias. We find that, although the I-V characteristics are ohmic at low Bias, the conduction becomes space charge limited at high V-DS, and existence of an exponential distribution of trap states was observed. The temperature independent critical Drain-source voltage (V-c) was also determined. The density of trap states was quantitatively calculated from V-c. The possible origin of exponential trap distribution in these devices is also discussed. (C) 2013 AIP Publishing LLC.
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trap assisted space charge limited transport in short channel mos2 transistor
arXiv: Mesoscale and Nanoscale Physics, 2013Co-Authors: Subhamoy Ghatak, Arindam GhoshAbstract:We present temperature dependent $I-V$ measurements of short channel MoS$_2$ field effect devices at high source-Drain Bias. We find that although the $I-V$ characteristics are Ohmic at low Bias, the conduction becomes space charge limited at high $V_{DS}$ and existence of an exponential distribution of trap states was observed. The temperature independent critical Drain-source voltage ($V_c$) was also determined. The density of trap states was quantitatively calculated from $V_c$. The possible origin of exponential trap distribution in these devices is also discussed.