The Experts below are selected from a list of 43689 Experts worldwide ranked by ideXlab platform
Jongsun Park - One of the best experts on this subject based on the ideXlab platform.
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A Charge-Recycling Assist Technique for Reliable and Low Power SRAM Design
IEEE Transactions on Circuits and Systems I: Regular Papers, 2016Co-Authors: Woong Gil Choi, Jongsun ParkAbstract:This paper presents a novel charge-recycling SRAM assist circuit to reduce the Dynamic Power Consumption of SRAM assist technique. By collaboratively combining the read and write assist schemes, the wasted charge in conventional read assist circuit can be efficiently recycled in write assist technique. In order to compare the Dynamic Power Consumption at ISO minimum operating voltage $({V}_{\mathrm{MIN}})$ condition, the most probable failure point (MPFP) simulations are performed using 14 nm FinFET technology model. Compared to the conventional assist schemes, thanks to the charge-recycling, 41% Power saving, and 2.3% area reduction can be achieved by using the proposed SRAM assist circuit.
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a reconfigurable fir filter architecture to trade off filter performance for Dynamic Power Consumption
IEEE Transactions on Very Large Scale Integration Systems, 2011Co-Authors: Seokjae Lee, Jiwoong Choi, Seon Wook Kim, Jongsun ParkAbstract:This paper presents an architectural approach to the design of low Power reconfigurable finite impulse response (FIR) filter. The approach is well suited when the filter order is fixed and not changed for particular applications, and efficient trade-off between Power savings and filter performance can be made using the proposed architecture. Generally, FIR filter has large amplitude variations in input data and coefficients. Considering the amplitude of both the filter coefficients and inputs, the proposed FIR filter Dynamically changes the filter order. Mathematical analysis on Power savings and filter performance degradation and its experimental results show that the proposed approach achieves significant Power savings without seriously compromising the filter performance. The Power savings is up to 41.9% with minor performance degradation, and the area overhead of the proposed scheme is less than 5.3% compared to the conventional approach.
T. Srinivas - One of the best experts on this subject based on the ideXlab platform.
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A Reconfigurable FIR Filter Architecture of FIR Filter Performance for Dynamic Power Consumption
International Journal of Research, 2018Co-Authors: Sd.jaki Sharif, T. SrinivasAbstract:Transpose form finite-impulse response (FIR) filters are inherently pipelined and support multiple constant multiplications (MCM) technique that results in significant saving of computation. However, transpose form configuration does not directly support the block processing unlike direct-form configuration. In this paper, we explore the possibility of realization of block FIR filter in transpose form configuration for area-delay efficient realization of large order FIR filters for both fixed and reconfigurable applications. Based on a detailed computational analysis of transpose form configuration of FIR filter, we have derived a flow graph for transpose form block FIR filter with optimized register complexity. A generalized block formulation is presented for transpose form FIR filter. We have derived a general multiplier-based architecture for the proposed transpose form block filter for reconfigurable applications. A low-complexity design using the MCM scheme is also presented for the block implementation of fixed FIR filters. The proposed structure involves significantly less area delay product (ADP) and less energy per sample (EPS) than the existing block implementation of direct-form structure for medium or large filter lengths, while for the short-length filters, the block implementation of direct-form FIR structure has less ADP and less EPS than the proposed structure. Application specific integrated circuit synthesis result shows that the proposed structure for block size 4 and filter length 64 involves 42% less ADP and 40% less EPS than the best available FIR filter structure proposed for reconfigurable applications. For the same filter length and the same block size, the proposed structure involves 13% less ADP and 12.8% less EPS than those of the existing direct-form block FIR structure. The proposed architecture of this paper analysis the logic size, area and Power Consumption using Xilinx.
N. Chabini - One of the best experts on this subject based on the ideXlab platform.
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Reducing Dynamic Power Consumption in synchronous sequential digital designs using retiming and supply voltage scaling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2004Co-Authors: N. Chabini, Wayne WolfAbstract:The problem of minimizing Dynamic Power Consumption by scaling down the supply voltage of computational elements off critical paths is widely addressed in the literature for the case of combinational designs. The problem is NP-hard in general. To address the problem in the case of synchronous sequential digital designs, one needs to move some registers while applying voltage scaling. Moving these registers shifts some computational elements from critical paths, and can be done by basic retiming. Integrating basic retiming and supply voltage scaling to address this NP-hard problem cannot in general be done in polynomial run time. In this paper, we propose to first apply a guided retiming and then to apply supply voltage scaling on the retimed design. We devise new polynomial time algorithms to realize this guided retiming, and the supply voltage scaling on the retimed design. Also, we show that the problem in the case of combinational designs is not NP-hard for some combinational circuits with certain structure, and give a polynomial time algorithm to optimally solve it. Methods to determine lower bounds on the optimal reduction of Dynamic Power Consumption are also provided. Experimental results on known benchmarks have shown that the proposed approach can reduce Dynamic Power Consumption by factors as high as 61% for single-phase designs with minimal clock period. Also, they have shown that it can solve optimally the problem, and produce converter-free designs with reduced Dynamic Power Consumption. For large size circuits from ISCAS'89 benchmark suite, the proposed algorithms run in 15 s-1 h.
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unification of basic retiming and supply voltage scaling to minimize Dynamic Power Consumption for synchronous digital designs
Great Lakes Symposium on VLSI, 2003Co-Authors: N. Chabini, Ismail Chabini, E M Aboulhamid, Yvon SavariaAbstract:We address the problem of minimizing Dynamic Power Consumption for single-phase synchronous digital designs, under timing constraints, using an unification of basic retiming and supply voltage scaling. We assume that the number of supply voltages and their values are known for each computation element. Our main objective is then to change the location of registers using basic retiming while maximizing the number of computation elements off critical paths that can operate under a low available supply voltage, and can lead to a maximum Dynamic Power saving. We address the problem at the system-level. We formulate the problem as a Mixed Integer Linear Program (MILP). The exact optimal solution for the problem is then guaranteed. We also devise an algorithm to compute bounds on the values assigned by basic retiming to each computational element. Besides helping to find the optimal solution to the problem, these bounds also allow to reduce the run-time for finding this solution. The proposed approach can produce converter-free designs and can also minimize short-circuit Power Consumption. Experimental results have shown that Dynamic Power Consumption can be reduced by factors that range from 2.78% to 37.24% for single-phase designs with minimal clock period. For these experimental results, the run-time for solving the MILP is under 2min.
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ACM Great Lakes Symposium on VLSI - Unification of basic retiming and supply voltage scaling to minimize Dynamic Power Consumption for synchronous digital designs
Proceedings of the 13th ACM Great Lakes Symposium on VLSI - GLSVLSI '03, 2003Co-Authors: N. Chabini, Ismail Chabini, E M Aboulhamid, Yvon SavariaAbstract:We address the problem of minimizing Dynamic Power Consumption for single-phase synchronous digital designs, under timing constraints, using an unification of basic retiming and supply voltage scaling. We assume that the number of supply voltages and their values are known for each computation element. Our main objective is then to change the location of registers using basic retiming while maximizing the number of computation elements off critical paths that can operate under a low available supply voltage, and can lead to a maximum Dynamic Power saving. We address the problem at the system-level. We formulate the problem as a Mixed Integer Linear Program (MILP). The exact optimal solution for the problem is then guaranteed. We also devise an algorithm to compute bounds on the values assigned by basic retiming to each computational element. Besides helping to find the optimal solution to the problem, these bounds also allow to reduce the run-time for finding this solution. The proposed approach can produce converter-free designs and can also minimize short-circuit Power Consumption. Experimental results have shown that Dynamic Power Consumption can be reduced by factors that range from 2.78% to 37.24% for single-phase designs with minimal clock period. For these experimental results, the run-time for solving the MILP is under 2min.
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Methods for minimizing Dynamic Power Consumption in synchronous designs with multiple supply voltages
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2003Co-Authors: N. Chabini, Ismail Chabini, E M Aboulhamid, Yvon SavariaAbstract:We address the problem of minimizing Dynamic Power Consumption under performance constraints by scaling down the supply voltage of computational elements off critical paths. We assume that the number of possible supply voltages and their values are known for each computational element. We focus on solving this problem on cyclic and acyclic graphs corresponding to synchronous designs. We consider multiphase clocked sequential circuits derived using software pipelining techniques. In this paper, we present exact and heuristic methods to solve the problem. The proposed methods take the form of mathematical programming formulations and their associated solution algorithms. The exact methods are based on a mixed integer linear programming formulation of the problem. The heuristic methods are based on linear programming formulations derived from the exact problem formulation. Solution methods are analyzed experimentally in terms of their run time and effectiveness in finding designs with lower Dynamic Power using circuits from the ISCAS89 benchmark suite. Power reduction factors as high as 69.75% were obtained compared to designs using the highest supply voltages. One of the heuristic methods leads to solutions that are near optimal, typically within 5% from the optimal solution. Low Dynamic-Power designs with no or a small number of level converters, are also obtained.
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ASP-DAC - An approach for reducing Dynamic Power Consumption in synchronous sequential digital designs
ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753), 1Co-Authors: N. Chabini, Wayne WolfAbstract:The problem of minimizing Dynamic Power Consumption by scaling down the supply voltage of computational elements off critical paths is widely addressed in the literature for the case of combinational designs. The problem is NP-hard in general. To address this problem in the case of synchronous sequential digital designs, one needs to move some registers while applying voltage scaling. Moving these registers shifts some computational elements from critical paths, and can be done by basic retiming. Integrating basic retiming and voltage scaling to address this NP-hard problem cannot in general be done in polynomial run-time. In this paper, we propose to first apply a guided retiming and then to apply supply voltage scaling on the retimed design. We devise new polynomial time algorithms to realize this guided retiming, and the supply voltage scaling on the retimed design. Experimental results on known benchmarks have shown that the proposed approach can reduce Dynamic Power Consumption by factors as high as 61% for single-phase designs with minimal clock period. Also, they have shown that it can solve optimally the problem, and produce converter-free designs with reduced Dynamic Power Consumption. For larger size circuits from ISCAS'89 benchmark suite, the proposed algorithms run in 15s-1h.
Sd.jaki Sharif - One of the best experts on this subject based on the ideXlab platform.
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A Reconfigurable FIR Filter Architecture of FIR Filter Performance for Dynamic Power Consumption
International Journal of Research, 2018Co-Authors: Sd.jaki Sharif, T. SrinivasAbstract:Transpose form finite-impulse response (FIR) filters are inherently pipelined and support multiple constant multiplications (MCM) technique that results in significant saving of computation. However, transpose form configuration does not directly support the block processing unlike direct-form configuration. In this paper, we explore the possibility of realization of block FIR filter in transpose form configuration for area-delay efficient realization of large order FIR filters for both fixed and reconfigurable applications. Based on a detailed computational analysis of transpose form configuration of FIR filter, we have derived a flow graph for transpose form block FIR filter with optimized register complexity. A generalized block formulation is presented for transpose form FIR filter. We have derived a general multiplier-based architecture for the proposed transpose form block filter for reconfigurable applications. A low-complexity design using the MCM scheme is also presented for the block implementation of fixed FIR filters. The proposed structure involves significantly less area delay product (ADP) and less energy per sample (EPS) than the existing block implementation of direct-form structure for medium or large filter lengths, while for the short-length filters, the block implementation of direct-form FIR structure has less ADP and less EPS than the proposed structure. Application specific integrated circuit synthesis result shows that the proposed structure for block size 4 and filter length 64 involves 42% less ADP and 40% less EPS than the best available FIR filter structure proposed for reconfigurable applications. For the same filter length and the same block size, the proposed structure involves 13% less ADP and 12.8% less EPS than those of the existing direct-form block FIR structure. The proposed architecture of this paper analysis the logic size, area and Power Consumption using Xilinx.
Paul V Gratz - One of the best experts on this subject based on the ideXlab platform.
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exploiting zero data to reduce register file and execution unit Dynamic Power Consumption in gpgpus
Design Automation Conference, 2020Co-Authors: Ahmad M Radaideh, Paul V GratzAbstract:To achieve high compute performance, graphics processing units (GPUs) provide a large register file and a large number of execution units. However, these design components consume a large portion of the total Dynamic Power in the GPU, particularly for general purpose applications. In this paper, we present a low-cost gating scheme to reduce Dynamic Power Consumption in the register file and execution units without impacting performance. The scheme proposed Dynamically exploit frequent found data value of zeros within and across registers in order to gate off register file reads and writes as well as execution units. We find that on general purpose applications from Rodinia, our low-cost gating scheme can reduce register file reads and writes on average by 35% and 40%, respectively. The register file and execution unit Dynamic Power are reduced on average by 19% and 13%, respectively. The reduction in total GPU Dynamic Power achieved is ranging from 3% to 19% with 8% on average with no performance loss.
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DAC - Exploiting Zero Data to Reduce Register File and Execution Unit Dynamic Power Consumption in GPGPUs
2020 57th ACM IEEE Design Automation Conference (DAC), 2020Co-Authors: Ahmad M Radaideh, Paul V GratzAbstract:To achieve high compute performance, graphics processing units (GPUs) provide a large register file and a large number of execution units. However, these design components consume a large portion of the total Dynamic Power in the GPU, particularly for general purpose applications. In this paper, we present a low-cost gating scheme to reduce Dynamic Power Consumption in the register file and execution units without impacting performance. The scheme proposed Dynamically exploit frequent found data value of zeros within and across registers in order to gate off register file reads and writes as well as execution units. We find that on general purpose applications from Rodinia, our low-cost gating scheme can reduce register file reads and writes on average by 35% and 40%, respectively. The register file and execution unit Dynamic Power are reduced on average by 19% and 13%, respectively. The reduction in total GPU Dynamic Power achieved is ranging from 3% to 19% with 8% on average with no performance loss.
