The Experts below are selected from a list of 7560 Experts worldwide ranked by ideXlab platform

Masahiro Fujita - One of the best experts on this subject based on the ideXlab platform.

  • formally analyzing fault tolerance in datapath designs using Equivalence Checking
    Asia and South Pacific Design Automation Conference, 2016
    Co-Authors: Payman Behnam, Bijan Alizadeh, Sajjad Taheri, Masahiro Fujita
    Abstract:

    In this paper, we present an efficient formal approach to check the Equivalence of synthesized Register Transfer Level (RTL) against the high level specification in the presence of pipelining transformations. With the proposed Equivalence Checking method, fault tolerance issues when some faults happen in the designs can be formally analyzed. Equivalence Checking with the specification can reason about how quickly the design can come back to normal operations when some faults happen. To increase the scalability of our proposed method, we dynamically divide the designs into several smaller parts called segments by introducing dynamic cut-points. Then we employ Modular Horner Expansion Diagram (M-HED) to check whether the specification and the implementation are equivalent or not. Our proposed method enables us to deal with the Equivalence Checking problem for behaviorally synthesized designs even in the presence of pipelines for nested loops. The empirical results demonstrate the efficiency and scalability of our proposed method in terms of run-time and memory usage for several large designs synthesized by a commercial behavioral synthesis tool. Average improvements in terms of the memory usage and run time in comparison with SMT- and SAT-based Equivalence Checking are 16.7× and 111.9×, respectively.

  • ASP-DAC - Formally analyzing fault tolerance in datapath designs using Equivalence Checking
    2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC), 2016
    Co-Authors: Payman Behnam, Bijan Alizadeh, Sajjad Taheri, Masahiro Fujita
    Abstract:

    In this paper, we present an efficient formal approach to check the Equivalence of synthesized Register Transfer Level (RTL) against the high level specification in the presence of pipelining transformations. With the proposed Equivalence Checking method, fault tolerance issues when some faults happen in the designs can be formally analyzed. Equivalence Checking with the specification can reason about how quickly the design can come back to normal operations when some faults happen. To increase the scalability of our proposed method, we dynamically divide the designs into several smaller parts called segments by introducing dynamic cut-points. Then we employ Modular Horner Expansion Diagram (M-HED) to check whether the specification and the implementation are equivalent or not. Our proposed method enables us to deal with the Equivalence Checking problem for behaviorally synthesized designs even in the presence of pipelines for nested loops. The empirical results demonstrate the efficiency and scalability of our proposed method in terms of run-time and memory usage for several large designs synthesized by a commercial behavioral synthesis tool. Average improvements in terms of the memory usage and run time in comparison with SMT- and SAT-based Equivalence Checking are 16.7× and 111.9×, respectively.

  • Word-Level Equivalence Checking in Bit-Level Accuracy by Synthesizing Designs onto Identical Datapath
    IEICE Transactions on Information and Systems, 2009
    Co-Authors: Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita
    Abstract:

    Equivalence Checking is one of the most important issues in VLSI design to guarantee that bugs do not enter designs during optimization steps or synthesis steps. In this paper, we propose a new word-level Equivalence Checking method between two models before and after high-level synthesis or behavioral optimization. Our method converts two given designs into RTL models which have same datapaths so that behaviors by identical control signals become the same in the two designs. Also, functional units become common to the two designs. Then word-level Equivalence Checking techniques can be applied in bit-level accuracy. In addition, we propose a rule-based Equivalence Checking method which can verify designs which have complicated control structures faster than existing symbolic simulation based methods. Experimental results with realistic examples show that our method can verify such designs in practical periods.

  • Rule-based Equivalence Checking of system-level design descriptions
    2009 International Conference on Communications Circuits and Systems, 2009
    Co-Authors: Hiroaki Yoshida, Masahiro Fujita
    Abstract:

    This paper presents our study on rule-based Equivalence Checking of system-level design descriptions. The rule-based Equivalence Checking proves the Equivalence of two system-level design descriptions by applying Equivalence rules in a bottom-up manner. In this paper, we first introduce our intermediate representation of system-level design, and then show a set of representative Equivalence rules. Since our Equivalence Checking method is based on potential internal Equivalences identified by using random simulation, we also present how to prove the Equivalence based on such potential internal Equivalences. Finally, we explain our implementation of the rule-based Equivalence checker and demonstrate its feasibility and efficiency using an example design.

  • Equivalence Checking of high-level designs based on symbolic simulation
    2009 International Conference on Communications Circuits and Systems, 2009
    Co-Authors: Takeshi Matsumoto, Tasuku Nishihara, Yoshihisa Kojima, Masahiro Fujita
    Abstract:

    In this paper, we present a formal Equivalence Checking method for source-to-source refinements in C-based high-level hardware design descriptions. The method is based on word-level symbolic simulation, where variables and operators in designs are treated as uninterpreted symbols. In addition, we introduce a more efficient method utilizing the difference between two designs under verification. It can verify the Equivalence faster when the similarity between the designs is large. We also show case studies of Equivalence Checking that were carried out with our verification framework FLEC.

Zeng Song-wei - One of the best experts on this subject based on the ideXlab platform.

  • Research on Storage Elements Mapping for Sequential Equivalence Checking
    Computer Science, 2009
    Co-Authors: Zeng Song-wei
    Abstract:

    As the integrated circuit size continues to increase,the complexity of system function has become increasingly high.Functional verification has become the bottleneck of the design flow.For large sequential circuits,the traditional sequential Equivalence Checking based on state-space traversal of product machine potentially meets with the state explosion.In order to improve the efficiency and the scalability of Equivalence Checking technology,by exploiting the storage element correspondence,the sequential Equivalence Checking may reduce to combinational Equivalence Checking,which is computationally less expensive.We investigated the basic method of sequential Equivalence Checking,and discussed the principle of storage element mapping.Then we introduced some typical mapping algorithms.Finally,the current and future research frontiers on Equivalence Checking were put forward.

Fei Xie - One of the best experts on this subject based on the ideXlab platform.

  • DATE - Equivalence Checking for function pipelining in behavioral synthesis
    Design Automation & Test in Europe Conference & Exhibition (DATE) 2014, 2014
    Co-Authors: Kecheng Hao, Sandip Ray, Fei Xie
    Abstract:

    Function pipelining is a key transformation in behavioral synthesis. However, synthesizing the complex pipeline logic is an error-prone process. Sequential Equivalence Checking (SEC) support is highly desired to provide confidence in the correctness of synthesized pipelines. However, SEC for function pipelining is challenging due to the significant difference between the behavioral specification and synthesized RTL. Furthermore, function pipelines include hardware logic for dynamically inserting “bubbles” (pipeline stalls), which bring additional difficulties in Equivalence Checking. We develop an SEC framework for behaviorally synthesized function pipelines by (1) building a reference pipeline model with a certified function pipelining transformation, which faithfully captures bubble insertion; and (2) Checking the Equivalence between the reference model and synthesized RTL. We demonstrate the scalability of our approach on industry-strength designs synthesized by a commercial tool.

  • handling design and implementation optimizations in Equivalence Checking for behavioral synthesis
    Design Automation Conference, 2013
    Co-Authors: Zhenkun Yang, Kecheng Hao, Sandip Ray, Fei Xie
    Abstract:

    Behavioral synthesis involves generating hardware design via compilation of its Electronic System Level (ESL) description to an RTL implementation. Equivalence Checking is critical to ensure that the synthesized RTL conforms to its ESL specification. Such Equivalence Checking must effectively handle design and implementation optimizations. We identify two key optimizations that complicate Equivalence Checking for behavioral synthesis: (1) operation gating, and (2) global variables. We develop a sequential Equivalence Checking (SEC) framework to compare ESL designs with RTL in the presence of these optimizations. Our approach can handle designs with more than 32K LoC RTL synthesized from practical ESL designs. Furthermore, our evaluation found a bug in a commercial tool, underlining both the importance of SEC and the effectiveness of our approach.

  • DAC - Handling design and implementation optimizations in Equivalence Checking for behavioral synthesis
    Proceedings of the 50th Annual Design Automation Conference on - DAC '13, 2013
    Co-Authors: Zhenkun Yang, Kecheng Hao, Sandip Ray, Fei Xie
    Abstract:

    Behavioral synthesis involves generating hardware design via compilation of its Electronic System Level (ESL) description to an RTL implementation. Equivalence Checking is critical to ensure that the synthesized RTL conforms to its ESL specification. Such Equivalence Checking must effectively handle design and implementation optimizations. We identify two key optimizations that complicate Equivalence Checking for behavioral synthesis: (1) operation gating, and (2) global variables. We develop a sequential Equivalence Checking (SEC) framework to compare ESL designs with RTL in the presence of these optimizations. Our approach can handle designs with more than 32K LoC RTL synthesized from practical ESL designs. Furthermore, our evaluation found a bug in a commercial tool, underlining both the importance of SEC and the effectiveness of our approach.

  • Equivalence Checking for behaviorally synthesized pipelines
    Design Automation Conference, 2012
    Co-Authors: Kecheng Hao, Sandip Ray, Fei Xie
    Abstract:

    Loop pipelining is a critical transformation in behavioral synthesis. It is crucial to producing hardware designs with acceptable latency and throughput. However, it is a complex transformation involving aggressive scheduling strategies for high throughput and careful control generation to eliminate hazards. We present an Equivalence Checking approach for certifying synthesized hardware designs in the presence of pipelining transformations. Our approach works by (1) constructing a provably correct pipeline reference model from sequential specification, and (2) applying sequential Equivalence Checking between this reference model and synthesized RTL. We demonstrate the scalability of our approach on several synthesized designs from a commercial synthesis tool.

  • DAC - Equivalence Checking for behaviorally synthesized pipelines
    Proceedings of the 49th Annual Design Automation Conference on - DAC '12, 2012
    Co-Authors: Kecheng Hao, Sandip Ray, Fei Xie
    Abstract:

    Loop pipelining is a critical transformation in behavioral synthesis. It is crucial to producing hardware designs with acceptable latency and throughput. However, it is a complex transformation involving aggressive scheduling strategies for high throughput and careful control generation to eliminate hazards. We present an Equivalence Checking approach for certifying synthesized hardware designs in the presence of pipelining transformations. Our approach works by (1) constructing a provably correct pipeline reference model from sequential specification, and (2) applying sequential Equivalence Checking between this reference model and synthesized RTL. We demonstrate the scalability of our approach on several synthesized designs from a commercial synthesis tool.

Weilun Hung - One of the best experts on this subject based on the ideXlab platform.

  • inductive Equivalence Checking under retiming and resynthesis
    International Conference on Computer Aided Design, 2007
    Co-Authors: Jiehong R Jiang, Weilun Hung
    Abstract:

    Retiming and resynthesis are among the most important techniques for practical sequential circuit optimization. However, their applicability is much limited due to verification concerns. Overcoming the verification bottleneck is a supreme task. This paper studies both the theoretical and practical aspects of inductive verification on the Equivalence between circuits under retiming and resynthesis transformation. We study the completeness condition of the inductive approach to Equivalence Checking and show that prior work is only complete for circuits transformed under retiming or resynthesis. but not both. We overcome prior limitation and make complete the Equivalence Checking for circuits transformed up to retiming+resynthesis-!-retiming. The theoretical insights lead to a robust satisfiability formulation of verification under various retiming and resynthesis scenarios. Experimental results demonstrate the scalability of the approach. Several previously unverifiable circuits and unverifiable transformation scenarios can now be verified effectively.

  • ICCAD - Inductive Equivalence Checking under retiming and resynthesis
    2007 IEEE ACM International Conference on Computer-Aided Design, 2007
    Co-Authors: Jiehong R Jiang, Weilun Hung
    Abstract:

    Retiming and resynthesis are among the most important techniques for practical sequential circuit optimization. However, their applicability is much limited due to verification concerns. Overcoming the verification bottleneck is a supreme task. This paper studies both the theoretical and practical aspects of inductive verification on the Equivalence between circuits under retiming and resynthesis transformation. We study the completeness condition of the inductive approach to Equivalence Checking and show that prior work is only complete for circuits transformed under retiming or resynthesis. but not both. We overcome prior limitation and make complete the Equivalence Checking for circuits transformed up to retiming+resynthesis-!-retiming. The theoretical insights lead to a robust satisfiability formulation of verification under various retiming and resynthesis scenarios. Experimental results demonstrate the scalability of the approach. Several previously unverifiable circuits and unverifiable transformation scenarios can now be verified effectively.

Kecheng Hao - One of the best experts on this subject based on the ideXlab platform.

  • DATE - Equivalence Checking for function pipelining in behavioral synthesis
    Design Automation & Test in Europe Conference & Exhibition (DATE) 2014, 2014
    Co-Authors: Kecheng Hao, Sandip Ray, Fei Xie
    Abstract:

    Function pipelining is a key transformation in behavioral synthesis. However, synthesizing the complex pipeline logic is an error-prone process. Sequential Equivalence Checking (SEC) support is highly desired to provide confidence in the correctness of synthesized pipelines. However, SEC for function pipelining is challenging due to the significant difference between the behavioral specification and synthesized RTL. Furthermore, function pipelines include hardware logic for dynamically inserting “bubbles” (pipeline stalls), which bring additional difficulties in Equivalence Checking. We develop an SEC framework for behaviorally synthesized function pipelines by (1) building a reference pipeline model with a certified function pipelining transformation, which faithfully captures bubble insertion; and (2) Checking the Equivalence between the reference model and synthesized RTL. We demonstrate the scalability of our approach on industry-strength designs synthesized by a commercial tool.

  • handling design and implementation optimizations in Equivalence Checking for behavioral synthesis
    Design Automation Conference, 2013
    Co-Authors: Zhenkun Yang, Kecheng Hao, Sandip Ray, Fei Xie
    Abstract:

    Behavioral synthesis involves generating hardware design via compilation of its Electronic System Level (ESL) description to an RTL implementation. Equivalence Checking is critical to ensure that the synthesized RTL conforms to its ESL specification. Such Equivalence Checking must effectively handle design and implementation optimizations. We identify two key optimizations that complicate Equivalence Checking for behavioral synthesis: (1) operation gating, and (2) global variables. We develop a sequential Equivalence Checking (SEC) framework to compare ESL designs with RTL in the presence of these optimizations. Our approach can handle designs with more than 32K LoC RTL synthesized from practical ESL designs. Furthermore, our evaluation found a bug in a commercial tool, underlining both the importance of SEC and the effectiveness of our approach.

  • DAC - Handling design and implementation optimizations in Equivalence Checking for behavioral synthesis
    Proceedings of the 50th Annual Design Automation Conference on - DAC '13, 2013
    Co-Authors: Zhenkun Yang, Kecheng Hao, Sandip Ray, Fei Xie
    Abstract:

    Behavioral synthesis involves generating hardware design via compilation of its Electronic System Level (ESL) description to an RTL implementation. Equivalence Checking is critical to ensure that the synthesized RTL conforms to its ESL specification. Such Equivalence Checking must effectively handle design and implementation optimizations. We identify two key optimizations that complicate Equivalence Checking for behavioral synthesis: (1) operation gating, and (2) global variables. We develop a sequential Equivalence Checking (SEC) framework to compare ESL designs with RTL in the presence of these optimizations. Our approach can handle designs with more than 32K LoC RTL synthesized from practical ESL designs. Furthermore, our evaluation found a bug in a commercial tool, underlining both the importance of SEC and the effectiveness of our approach.

  • Equivalence Checking for behaviorally synthesized pipelines
    Design Automation Conference, 2012
    Co-Authors: Kecheng Hao, Sandip Ray, Fei Xie
    Abstract:

    Loop pipelining is a critical transformation in behavioral synthesis. It is crucial to producing hardware designs with acceptable latency and throughput. However, it is a complex transformation involving aggressive scheduling strategies for high throughput and careful control generation to eliminate hazards. We present an Equivalence Checking approach for certifying synthesized hardware designs in the presence of pipelining transformations. Our approach works by (1) constructing a provably correct pipeline reference model from sequential specification, and (2) applying sequential Equivalence Checking between this reference model and synthesized RTL. We demonstrate the scalability of our approach on several synthesized designs from a commercial synthesis tool.

  • DAC - Equivalence Checking for behaviorally synthesized pipelines
    Proceedings of the 49th Annual Design Automation Conference on - DAC '12, 2012
    Co-Authors: Kecheng Hao, Sandip Ray, Fei Xie
    Abstract:

    Loop pipelining is a critical transformation in behavioral synthesis. It is crucial to producing hardware designs with acceptable latency and throughput. However, it is a complex transformation involving aggressive scheduling strategies for high throughput and careful control generation to eliminate hazards. We present an Equivalence Checking approach for certifying synthesized hardware designs in the presence of pipelining transformations. Our approach works by (1) constructing a provably correct pipeline reference model from sequential specification, and (2) applying sequential Equivalence Checking between this reference model and synthesized RTL. We demonstrate the scalability of our approach on several synthesized designs from a commercial synthesis tool.