The Experts below are selected from a list of 248868 Experts worldwide ranked by ideXlab platform
Lan-rong Dung - One of the best experts on this subject based on the ideXlab platform.
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Verification method of dataflow algorithms in high-Level Synthesis
Journal of Systems and Software, 2007Co-Authors: Tsung-hsi Chiang, Lan-rong DungAbstract:This paper presents a formal verification algorithm using the Petri Net theory to detect design errors for high-Level Synthesis of dataflow algorithms. Typically, given a dataflow algorithm and a set of architectural constraints, the high-Level Synthesis performs algorithmic transformation and produces the optimal scheduling. How to verify the correctness of high-Level Synthesis becomes a key issue before mapping the Synthesis results onto a silicon. Many tools exist for RTL (Register Transfer Level) design, but few for high-Level Synthesis. Instead of applying Boolean algebra, this paper adopts the Petri Net theory to verify the correctness of the Synthesis result, because the Petri Net model has the nature of dataflow algorithms. Herein, we propose three approaches to realize the Petri Net based formal verification algorithm and conclude the best one who outperforms the others in terms of processing speed and resource usage.
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ISCAS - System-Level verification on high-Level Synthesis of dataflow graph
2006 IEEE International Symposium on Circuits and Systems, 1Co-Authors: Tsung-hsi Chiang, Lan-rong DungAbstract:This paper presents a system-Level verification algorithm using the Petri net theory to detect design errors for high-Level Synthesis of dataflow graphs. Typically, given a dataflow graph and a set of architectural constraints, the high-Level Synthesis performs algorithmic transformation and produces the optimal scheduling. How to verify the correctness of high-Level Synthesis becomes a key issue before mapping the Synthesis results onto silicon. Many tools exist for RTL design, but few for high-Level Synthesis. Instead of applying Boolean algebra, this paper adopts the Petri net theory to verify the correctness of the Synthesis result. Herein, we propose three approaches to realize the Petri net based formal verification algorithm and identify the best one that outperforms the others in terms of processing speed and resource usage.
M. Joseph - One of the best experts on this subject based on the ideXlab platform.
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Recent Developments in Scheduling and Allocation of High Level Synthesis
Lecture Notes of the Institute for Computer Sciences Social Informatics and Telecommunications Engineering, 2012Co-Authors: M. Chinnadurai, M. JosephAbstract:We survey the recent developments of scheduling and allocation techniques in high Level Synthesis. Technology driven High-Level Synthesis is a customized high-Level Synthesis tool to make an optimal hardware generation, it makes the present knowledgeable of the target Field Programmable Gate Array. We then describe the different techniques and applications of different scheduling and allocation concepts in high Level Synthesis. To maximize the benefits of HLS, this paper describes the scheduling and allocation algorithms using Technology Specific Library (TSL).
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Survey on Optimization Techniques in High Level Synthesis
Lecture Notes of the Institute for Computer Sciences Social Informatics and Telecommunications Engineering, 2012Co-Authors: B. Saravanakumaran, M. JosephAbstract:This paper provides a detailed survey of optimization techniques available in high Level Synthesis. This survey contemplates on two parts. The first part deals with the applicability of optimization techniques available in high Level language compiler into high Level Synthesis. The second part address the topics such as Area optimization, Resource optimization, Power optimization and Optimization issues pertaining to the notions value-grouping, value to register assignment, Transfer to wire assignment and wire to FU port assignment.
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Floating-Point Adder in Techology Driven High-Level Synthesis
Advances in Computer Science and Information Technology, 2011Co-Authors: M. Joseph, Narasimha B. Bhat, K. Chandra SekaranAbstract:Implementation of floating-point algorithms in fixed-point processor asks for customization into fixed-point for that processor. Technology driven High-Level Synthesis is a customized High-Level Synthesis approach for a particular fixed-point processor. It makes the present High-Level Synthesis knowledgeable of the target Field Programmable Gate Array. All the functions of High-Level Synthesis become aware of target technology since parsing here. It makes right inference of hardware by attaching target technology specific attributes to the parse tree in it, which guides to generate optimized hardware. This paper, integrating both, presents an approach to synthesize the floating-point algorithms in this customized tool. It performs the conversion of floating-point model into corresponding fixed-point model and synthesizes it for implementing onto an Field Programmable Gate Array. This compiler driven approach generates optimal output in terms of silicon usage and power consumption.
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Technology driven High-Level Synthesis
15th International Conference on Advanced Computing and Communications (ADCOM 2007), 2007Co-Authors: M. Joseph, Narasimha B. Bhat, K. Chandra SekaranAbstract:present High-Level Synthesis knowledgeable of the target Field Programmable Gate Array. All the functions of High-Level Syn- thesis become aware of target technology since parsing. It makes right inference of hardware, by attaching target technology specific attributes to the parse tree. This right inference will guide to generate optimized hardware. Keywords: High-Level Synthesis, Target Technology, At- tribute Grammars, Optimization, FPGA.
C.a. Papachristou - One of the best experts on this subject based on the ideXlab platform.
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Rescheduling transformations for high Level Synthesis
IEEE International Symposium on Circuits and Systems, 1Co-Authors: C.a. PapachristouAbstract:A new approach is presented to high-Level Synthesis with self-testability. The motivation for this work is the need to fill the void between the fields of high-Level Synthesis and design for testability. The approach is based on a new allocation algorithm that maps a scheduled data-flow representation of the behavior into a data-path structure that is testable, with no need for test hardware insertion. An important feature of the approach is the rescheduling of transformations to perform design space exploration, under area, delay, and testability constraints. A significant advantage of this method is that the testability design is well integrated into the framework of high-Level Synthesis at the behavior Level. >
Tsung-hsi Chiang - One of the best experts on this subject based on the ideXlab platform.
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Verification method of dataflow algorithms in high-Level Synthesis
Journal of Systems and Software, 2007Co-Authors: Tsung-hsi Chiang, Lan-rong DungAbstract:This paper presents a formal verification algorithm using the Petri Net theory to detect design errors for high-Level Synthesis of dataflow algorithms. Typically, given a dataflow algorithm and a set of architectural constraints, the high-Level Synthesis performs algorithmic transformation and produces the optimal scheduling. How to verify the correctness of high-Level Synthesis becomes a key issue before mapping the Synthesis results onto a silicon. Many tools exist for RTL (Register Transfer Level) design, but few for high-Level Synthesis. Instead of applying Boolean algebra, this paper adopts the Petri Net theory to verify the correctness of the Synthesis result, because the Petri Net model has the nature of dataflow algorithms. Herein, we propose three approaches to realize the Petri Net based formal verification algorithm and conclude the best one who outperforms the others in terms of processing speed and resource usage.
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ISCAS - System-Level verification on high-Level Synthesis of dataflow graph
2006 IEEE International Symposium on Circuits and Systems, 1Co-Authors: Tsung-hsi Chiang, Lan-rong DungAbstract:This paper presents a system-Level verification algorithm using the Petri net theory to detect design errors for high-Level Synthesis of dataflow graphs. Typically, given a dataflow graph and a set of architectural constraints, the high-Level Synthesis performs algorithmic transformation and produces the optimal scheduling. How to verify the correctness of high-Level Synthesis becomes a key issue before mapping the Synthesis results onto silicon. Many tools exist for RTL design, but few for high-Level Synthesis. Instead of applying Boolean algebra, this paper adopts the Petri net theory to verify the correctness of the Synthesis result. Herein, we propose three approaches to realize the Petri net based formal verification algorithm and identify the best one that outperforms the others in terms of processing speed and resource usage.
Gi-yong Song - One of the best experts on this subject based on the ideXlab platform.
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High-Level Synthesis Using SPARK and Systolic Array
Lecture Notes in Computer Science, 2006Co-Authors: Jae-jin Lee, Gi-yong SongAbstract:Recently, SPARK parallelizing high-Level Synthesis software tool has been developed. It takes a behavioral ANSI-C code as an input, schedules it using speculative code motions and loop transformations, generates a finite state machine for the sclieduled design graph, and then finally outputs a synthesizable RTL VHDL code. To handle loop algorithm, SPARK employs various loop transformations such as loop invariant code motion, loop unrolling, loop index variable elimination and loop shifting. In loop Synthesis, however, SPARK does not produce circuit description whose quality can compete with manual designs. With the objective of improving the quality of high-Level Synthesis results for designs with loops, this paper shows an upgrade of SPARK through transforming nested loops into a 2-D systolic array to increase parallelism. The C-to-VHDL loop Synthesis in this paper achieves Synthesis results that are better than those achieved from a current version of SPARK for matrix-matrix multiplication and FIR filter, and can be incorporated into SPARK parallelizing high-Level Synthesis framework.
