The Experts below are selected from a list of 2208 Experts worldwide ranked by ideXlab platform
T. P. - One of the best experts on this subject based on the ideXlab platform.
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SONOS-Type Flash Memory Cell With Metal Structure for Low-Voltage High-Speed Program/Erase Operation
IEEE Electron Device Letters, 2008Co-Authors: Sun Il Shim, X. W. Wang, T. P.Abstract:High-quality Al2O3 and Si3N4 dielectrics synthesized in a molecular/atomic deposition system were developed and adopted as blocking oxide and tunnel dielectric, respectively in a SONOS-type NAND flash memory cell. In particular, the use of trap-free Si3N4 as tunnel dielectric enables low-voltage Erase Operation due to its low barrier height for holes, and the relatively high-k value of Al2O3 enhances the low-voltage and high-speed program/Erase (P/E) Operations. We fabricated and investigated NAND flash memory cells with metal/Al2O3/SiN/Si3N4/Si structure. The fabricated cell shows 3.8-V memory window with P/E conditions of +15 V for 100 mus and -10 V for 10 ms. It also shows good endurance up to 10 000 cycles and more than 1.5-V memory window after ten years.
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sonos type flash memory cell with metal al _ 2 o _ 3 sin si _ 3 n _ 4 si structure for low voltage high speed program Erase Operation
IEEE Electron Device Letters, 2008Co-Authors: Sun Il Shim, X. W. Wang, T. P.Abstract:High-quality Al2O3 and Si3N4 dielectrics synthe- sized in a molecular/atomic deposition system were developed and adopted as blocking oxide and tunnel dielectric, respectively in a SONOS-type NAND flash memory cell. In particular, the use of trap-free Si3N4 as tunnel dielectric enables low-voltage Erase Operation due to its low barrier height for holes, and the relatively high-k value of Al2O3 enhances the low-voltage and high-speed program/Erase (P/E) Operations. We fabricated and investigated NAND flash memory cells with metal/Al2O3/SiN/Si3N4/Si struc- ture. The fabricated cell shows 3.8-V memory window with P/E conditions of +15 V for 100 µ sa nd−10 V for 10 ms. It also shows good endurance up to 10 000 cycles and more than 1.5-V memory window after ten years. Index Terms—Aluminum oxide, charge trap (CT), flash memory, metal/Al2O3/SiN/Si3N4/Si (MANNS), silicon nitride, SONOS, TANOS.
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sonos type flash memory cell with metal hbox al _ 2 hbox o _ 3 hbox sin hbox si _ 3 hbox n _ 4 hbox si structure for low voltage high speed program Erase Operation
IEEE Electron Device Letters, 2008Co-Authors: Sun Il Shim, X. W. Wang, T. P.Abstract:High-quality Al2O3 and Si3N4 dielectrics synthesized in a molecular/atomic deposition system were developed and adopted as blocking oxide and tunnel dielectric, respectively in a SONOS-type NAND flash memory cell. In particular, the use of trap-free Si3N4 as tunnel dielectric enables low-voltage Erase Operation due to its low barrier height for holes, and the relatively high-k value of Al2O3 enhances the low-voltage and high-speed program/Erase (P/E) Operations. We fabricated and investigated NAND flash memory cells with metal/Al2O3/SiN/Si3N4/Si structure. The fabricated cell shows 3.8-V memory window with P/E conditions of +15 V for 100 mus and -10 V for 10 ms. It also shows good endurance up to 10 000 cycles and more than 1.5-V memory window after ten years.
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SONOS-Type Flash Memory Cell With Metal $/\hbox{Al}_{2}\hbox{O}_{3}/ \hbox{SiN}/\hbox{Si}_{3}\hbox{N}_{4}/\hbox{Si}$ Structure for Low-Voltage High-Speed Program/Erase Operation
IEEE Electron Device Letters, 2008Co-Authors: Sun Il Shim, X. W. Wang, T. P.Abstract:High-quality Al2O3 and Si3N4 dielectrics synthesized in a molecular/atomic deposition system were developed and adopted as blocking oxide and tunnel dielectric, respectively in a SONOS-type NAND flash memory cell. In particular, the use of trap-free Si3N4 as tunnel dielectric enables low-voltage Erase Operation due to its low barrier height for holes, and the relatively high-k value of Al2O3 enhances the low-voltage and high-speed program/Erase (P/E) Operations. We fabricated and investigated NAND flash memory cells with metal/Al2O3/SiN/Si3N4/Si structure. The fabricated cell shows 3.8-V memory window with P/E conditions of +15 V for 100 mus and -10 V for 10 ms. It also shows good endurance up to 10 000 cycles and more than 1.5-V memory window after ten years.
Sun Il Shim - One of the best experts on this subject based on the ideXlab platform.
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SONOS-Type Flash Memory Cell With Metal Structure for Low-Voltage High-Speed Program/Erase Operation
IEEE Electron Device Letters, 2008Co-Authors: Sun Il Shim, X. W. Wang, T. P.Abstract:High-quality Al2O3 and Si3N4 dielectrics synthesized in a molecular/atomic deposition system were developed and adopted as blocking oxide and tunnel dielectric, respectively in a SONOS-type NAND flash memory cell. In particular, the use of trap-free Si3N4 as tunnel dielectric enables low-voltage Erase Operation due to its low barrier height for holes, and the relatively high-k value of Al2O3 enhances the low-voltage and high-speed program/Erase (P/E) Operations. We fabricated and investigated NAND flash memory cells with metal/Al2O3/SiN/Si3N4/Si structure. The fabricated cell shows 3.8-V memory window with P/E conditions of +15 V for 100 mus and -10 V for 10 ms. It also shows good endurance up to 10 000 cycles and more than 1.5-V memory window after ten years.
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sonos type flash memory cell with metal al _ 2 o _ 3 sin si _ 3 n _ 4 si structure for low voltage high speed program Erase Operation
IEEE Electron Device Letters, 2008Co-Authors: Sun Il Shim, X. W. Wang, T. P.Abstract:High-quality Al2O3 and Si3N4 dielectrics synthe- sized in a molecular/atomic deposition system were developed and adopted as blocking oxide and tunnel dielectric, respectively in a SONOS-type NAND flash memory cell. In particular, the use of trap-free Si3N4 as tunnel dielectric enables low-voltage Erase Operation due to its low barrier height for holes, and the relatively high-k value of Al2O3 enhances the low-voltage and high-speed program/Erase (P/E) Operations. We fabricated and investigated NAND flash memory cells with metal/Al2O3/SiN/Si3N4/Si struc- ture. The fabricated cell shows 3.8-V memory window with P/E conditions of +15 V for 100 µ sa nd−10 V for 10 ms. It also shows good endurance up to 10 000 cycles and more than 1.5-V memory window after ten years. Index Terms—Aluminum oxide, charge trap (CT), flash memory, metal/Al2O3/SiN/Si3N4/Si (MANNS), silicon nitride, SONOS, TANOS.
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sonos type flash memory cell with metal hbox al _ 2 hbox o _ 3 hbox sin hbox si _ 3 hbox n _ 4 hbox si structure for low voltage high speed program Erase Operation
IEEE Electron Device Letters, 2008Co-Authors: Sun Il Shim, X. W. Wang, T. P.Abstract:High-quality Al2O3 and Si3N4 dielectrics synthesized in a molecular/atomic deposition system were developed and adopted as blocking oxide and tunnel dielectric, respectively in a SONOS-type NAND flash memory cell. In particular, the use of trap-free Si3N4 as tunnel dielectric enables low-voltage Erase Operation due to its low barrier height for holes, and the relatively high-k value of Al2O3 enhances the low-voltage and high-speed program/Erase (P/E) Operations. We fabricated and investigated NAND flash memory cells with metal/Al2O3/SiN/Si3N4/Si structure. The fabricated cell shows 3.8-V memory window with P/E conditions of +15 V for 100 mus and -10 V for 10 ms. It also shows good endurance up to 10 000 cycles and more than 1.5-V memory window after ten years.
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SONOS-Type Flash Memory Cell With Metal $/\hbox{Al}_{2}\hbox{O}_{3}/ \hbox{SiN}/\hbox{Si}_{3}\hbox{N}_{4}/\hbox{Si}$ Structure for Low-Voltage High-Speed Program/Erase Operation
IEEE Electron Device Letters, 2008Co-Authors: Sun Il Shim, X. W. Wang, T. P.Abstract:High-quality Al2O3 and Si3N4 dielectrics synthesized in a molecular/atomic deposition system were developed and adopted as blocking oxide and tunnel dielectric, respectively in a SONOS-type NAND flash memory cell. In particular, the use of trap-free Si3N4 as tunnel dielectric enables low-voltage Erase Operation due to its low barrier height for holes, and the relatively high-k value of Al2O3 enhances the low-voltage and high-speed program/Erase (P/E) Operations. We fabricated and investigated NAND flash memory cells with metal/Al2O3/SiN/Si3N4/Si structure. The fabricated cell shows 3.8-V memory window with P/E conditions of +15 V for 100 mus and -10 V for 10 ms. It also shows good endurance up to 10 000 cycles and more than 1.5-V memory window after ten years.
X. W. Wang - One of the best experts on this subject based on the ideXlab platform.
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SONOS-Type Flash Memory Cell With Metal Structure for Low-Voltage High-Speed Program/Erase Operation
IEEE Electron Device Letters, 2008Co-Authors: Sun Il Shim, X. W. Wang, T. P.Abstract:High-quality Al2O3 and Si3N4 dielectrics synthesized in a molecular/atomic deposition system were developed and adopted as blocking oxide and tunnel dielectric, respectively in a SONOS-type NAND flash memory cell. In particular, the use of trap-free Si3N4 as tunnel dielectric enables low-voltage Erase Operation due to its low barrier height for holes, and the relatively high-k value of Al2O3 enhances the low-voltage and high-speed program/Erase (P/E) Operations. We fabricated and investigated NAND flash memory cells with metal/Al2O3/SiN/Si3N4/Si structure. The fabricated cell shows 3.8-V memory window with P/E conditions of +15 V for 100 mus and -10 V for 10 ms. It also shows good endurance up to 10 000 cycles and more than 1.5-V memory window after ten years.
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sonos type flash memory cell with metal al _ 2 o _ 3 sin si _ 3 n _ 4 si structure for low voltage high speed program Erase Operation
IEEE Electron Device Letters, 2008Co-Authors: Sun Il Shim, X. W. Wang, T. P.Abstract:High-quality Al2O3 and Si3N4 dielectrics synthe- sized in a molecular/atomic deposition system were developed and adopted as blocking oxide and tunnel dielectric, respectively in a SONOS-type NAND flash memory cell. In particular, the use of trap-free Si3N4 as tunnel dielectric enables low-voltage Erase Operation due to its low barrier height for holes, and the relatively high-k value of Al2O3 enhances the low-voltage and high-speed program/Erase (P/E) Operations. We fabricated and investigated NAND flash memory cells with metal/Al2O3/SiN/Si3N4/Si struc- ture. The fabricated cell shows 3.8-V memory window with P/E conditions of +15 V for 100 µ sa nd−10 V for 10 ms. It also shows good endurance up to 10 000 cycles and more than 1.5-V memory window after ten years. Index Terms—Aluminum oxide, charge trap (CT), flash memory, metal/Al2O3/SiN/Si3N4/Si (MANNS), silicon nitride, SONOS, TANOS.
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sonos type flash memory cell with metal hbox al _ 2 hbox o _ 3 hbox sin hbox si _ 3 hbox n _ 4 hbox si structure for low voltage high speed program Erase Operation
IEEE Electron Device Letters, 2008Co-Authors: Sun Il Shim, X. W. Wang, T. P.Abstract:High-quality Al2O3 and Si3N4 dielectrics synthesized in a molecular/atomic deposition system were developed and adopted as blocking oxide and tunnel dielectric, respectively in a SONOS-type NAND flash memory cell. In particular, the use of trap-free Si3N4 as tunnel dielectric enables low-voltage Erase Operation due to its low barrier height for holes, and the relatively high-k value of Al2O3 enhances the low-voltage and high-speed program/Erase (P/E) Operations. We fabricated and investigated NAND flash memory cells with metal/Al2O3/SiN/Si3N4/Si structure. The fabricated cell shows 3.8-V memory window with P/E conditions of +15 V for 100 mus and -10 V for 10 ms. It also shows good endurance up to 10 000 cycles and more than 1.5-V memory window after ten years.
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SONOS-Type Flash Memory Cell With Metal $/\hbox{Al}_{2}\hbox{O}_{3}/ \hbox{SiN}/\hbox{Si}_{3}\hbox{N}_{4}/\hbox{Si}$ Structure for Low-Voltage High-Speed Program/Erase Operation
IEEE Electron Device Letters, 2008Co-Authors: Sun Il Shim, X. W. Wang, T. P.Abstract:High-quality Al2O3 and Si3N4 dielectrics synthesized in a molecular/atomic deposition system were developed and adopted as blocking oxide and tunnel dielectric, respectively in a SONOS-type NAND flash memory cell. In particular, the use of trap-free Si3N4 as tunnel dielectric enables low-voltage Erase Operation due to its low barrier height for holes, and the relatively high-k value of Al2O3 enhances the low-voltage and high-speed program/Erase (P/E) Operations. We fabricated and investigated NAND flash memory cells with metal/Al2O3/SiN/Si3N4/Si structure. The fabricated cell shows 3.8-V memory window with P/E conditions of +15 V for 100 mus and -10 V for 10 ms. It also shows good endurance up to 10 000 cycles and more than 1.5-V memory window after ten years.
Guo-wei Huang - One of the best experts on this subject based on the ideXlab platform.
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low frequency noise in sonos tft with a trigate nanowire structure under program Erase Operation
IEEE Electron Device Letters, 2012Co-Authors: Hsin-hui Hu, Yong-ren Jheng, Yung-chun Wu, Min-feng Hung, Guo-wei HuangAbstract:This letter investigates low-frequency noise (LFN) in polycrystalline silicon thin-film transistor (TFT) nonvolatile memory (NVM) under Fowler-Nordheim tunneling program/Erase (P/E) Operation. The NVM utilizes a silicon-oxide-nitride-oxide-silicon (SONOS)-type structure with a trigate multiple nanowire (NW) channels. The difference in the flicker noise (1/f) level between a multiple-channel NW device and a standard single-channel device became smaller after P/E cycling. The observation can be explained by the quantity of grain-boundary traps introduced by higher electric field at the NW corner during the P/E cycle, subsequently increasing the LFN level in the multiple NW SONOS-TFT.
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Low-Frequency Noise in SONOS-TFT With a Trigate Nanowire Structure Under Program/Erase Operation
IEEE Electron Device Letters, 2012Co-Authors: Hsin-hui Hu, Yong-ren Jheng, Yung-chun Wu, Min-feng Hung, Guo-wei HuangAbstract:This letter investigates low-frequency noise (LFN) in polycrystalline silicon thin-film transistor (TFT) nonvolatile memory (NVM) under Fowler-Nordheim tunneling program/Erase (P/E) Operation. The NVM utilizes a silicon-oxide-nitride-oxide-silicon (SONOS)-type structure with a trigate multiple nanowire (NW) channels. The difference in the flicker noise (1/f) level between a multiple-channel NW device and a standard single-channel device became smaller after P/E cycling. The observation can be explained by the quantity of grain-boundary traps introduced by higher electric field at the NW corner during the P/E cycle, subsequently increasing the LFN level in the multiple NW SONOS-TFT.
Weisheng Zhao - One of the best experts on this subject based on the ideXlab platform.
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high density nand like spin transfer torque memory with spin orbit torque Erase Operation
IEEE Electron Device Letters, 2018Co-Authors: Zhaohao Wang, Lei Zhang, Mengxing Wang, Zilu Wang, Youguang Zhang, Weisheng ZhaoAbstract:We present a NAND-like spintronics memory (NAND-SPIN) device for high-density non-volatile memory applications. Fast erasing and programming of magnetic tunnel junction (MTJ) are implemented with two unidirectional currents generating spin orbit torque (SOT) and spin transfer torque (STT), respectively. The asymmetric switching drawback of STT mechanism can be definitively overcome as only anti-parallel to parallel Operation happens for NAND-SPIN programming, which allows lower switching current, smaller access transistor, and reduced maximum write voltage across the MTJ. By sharing the SOT-induced Erase Operation in a nanowire, the area overhead due to the three-terminal structure can be also eliminated. Simulation results show that NAND-SPIN can achieve $\text {3}\sim \text {5}\times $ reduction in write energy compared to STT-MRAM, and $\text {2}\sim \text {4}\times $ less bit-cell area than SOT-MRAM at 28 nm node.
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High-Density NAND-Like Spin Transfer Torque Memory With Spin Orbit Torque Erase Operation
IEEE Electron Device Letters, 2018Co-Authors: Zhaohao Wang, Lei Zhang, Mengxing Wang, Zilu Wang, Youguang Zhang, Weisheng ZhaoAbstract:We present a NAND-like spintronics memory (NAND-SPIN) device for high-density non-volatile memory applications. Fast erasing and programming of magnetic tunnel junction (MTJ) are implemented with two unidirectional currents generating spin orbit torque (SOT) and spin transfer torque (STT), respectively. The asymmetric switching drawback of STT mechanism can be definitively overcome as only anti-parallel to parallel Operation happens for NAND-SPIN programming, which allows lower switching current, smaller access transistor, and reduced maximum write voltage across the MTJ. By sharing the SOT-induced Erase Operation in a nanowire, the area overhead due to the three-terminal structure can be also eliminated. Simulation results show that NAND-SPIN can achieve 3 ~ 5× reduction in write energy compared to STT-MRAM, and 2 ~ 4× less bit-cell area than SOT-MRAM at 28 nm node.