The Experts below are selected from a list of 300 Experts worldwide ranked by ideXlab platform
Sreejit Chakravarty - One of the best experts on this subject based on the ideXlab platform.
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VTS - Path delay Fault Simulation on large industrial designs
24th IEEE VLSI Test Symposium, 1Co-Authors: Suriyaprakash Natarajan, Srinivas Patil, Sreejit ChakravartyAbstract:Path delay Fault Simulation performance on multi-cycle delay paths common in industrial designs is discussed using paths from a large block in a microprocessor and a functional test vector suite. We profile Fault Simulation performance using a novel multi-cycle path delay Fault simulator. Our experiments show that path delay Fault Simulation run-time grows linearly with path list size. Contrary to commonly held notion that path delay Fault Simulation is more expensive than stuck-at Fault Simulation, our experiments show that performance of path delay Fault grading is comparable to that of stuck-at Fault grading. Finally, we propose and evaluate a heuristic that can improve path delay Fault Simulation performance and also aid in selection of tests for speed-limiting paths.
Suriyaprakash Natarajan - One of the best experts on this subject based on the ideXlab platform.
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VTS - Path delay Fault Simulation on large industrial designs
24th IEEE VLSI Test Symposium, 1Co-Authors: Suriyaprakash Natarajan, Srinivas Patil, Sreejit ChakravartyAbstract:Path delay Fault Simulation performance on multi-cycle delay paths common in industrial designs is discussed using paths from a large block in a microprocessor and a functional test vector suite. We profile Fault Simulation performance using a novel multi-cycle path delay Fault simulator. Our experiments show that path delay Fault Simulation run-time grows linearly with path list size. Contrary to commonly held notion that path delay Fault Simulation is more expensive than stuck-at Fault Simulation, our experiments show that performance of path delay Fault grading is comparable to that of stuck-at Fault grading. Finally, we propose and evaluate a heuristic that can improve path delay Fault Simulation performance and also aid in selection of tests for speed-limiting paths.
Srinivas Patil - One of the best experts on this subject based on the ideXlab platform.
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Parallel algorithms for test generation and Fault Simulation
1991Co-Authors: Srinivas PatilAbstract:With increase in complexity of digital circuits, it has become extremely important to detect Faults to ensure correct operation of a digital circuit. Since test generation and Fault Simulation for circuits of VLSI complexity can take a prohibitive amount of time, speeding up test generation and Fault Simulation algorithms by either using better uniprocessor heuristics or by using the tremendous computing power available on multiprocessors thus becomes important. The design and analysis of parallel algorithms for test generation and Fault Simulation are the focus of this thesis research. We first categorize various parallel processing techniques available for test generation and Fault Simulation. We then propose a parallel search method to overcome the deficiencies of inaccurate search heuristics. We show that this method not only results in faster execution of the test generation algorithm but also results in a better quality of the solution. We also propose a performance model to evaluate the parallel search technique. We then propose Fault partitioning techniques to speed up test generation for Faults which are relatively easy to detect. The objective of the Fault partitioning techniques is to maximize concurrency without affecting the quality of the overall solution. We propose load balancing techniques which try to minimize the processor idle time with very low communication overhead. We propose a performance model which takes into account the various trade-offs in exploiting parallelism in a test generation/Fault Simulation environment. Finally, we present a parallel test generation system for sequential circuits. A parallel search technique is used to accelerate test generation for hard to detect Faults, and a circuit partitioned approach is used to accelerate Fault Simulation.
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VTS - Path delay Fault Simulation on large industrial designs
24th IEEE VLSI Test Symposium, 1Co-Authors: Suriyaprakash Natarajan, Srinivas Patil, Sreejit ChakravartyAbstract:Path delay Fault Simulation performance on multi-cycle delay paths common in industrial designs is discussed using paths from a large block in a microprocessor and a functional test vector suite. We profile Fault Simulation performance using a novel multi-cycle path delay Fault simulator. Our experiments show that path delay Fault Simulation run-time grows linearly with path list size. Contrary to commonly held notion that path delay Fault Simulation is more expensive than stuck-at Fault Simulation, our experiments show that performance of path delay Fault grading is comparable to that of stuck-at Fault grading. Finally, we propose and evaluate a heuristic that can improve path delay Fault Simulation performance and also aid in selection of tests for speed-limiting paths.
C.a. Ryan - One of the best experts on this subject based on the ideXlab platform.
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An algorithm for parallel hardware accelerated switch level Fault Simulation
Proceedings of Southeastcon '93, 1Co-Authors: C.a. Ryan, Joseph G. TrontAbstract:The complexity and large Simulation time for switch level Fault Simulation has been addressed by performing two-dimensional parallel Fault Simulation using a parallel hardware accelerated Fault simulator (PHAFS). The authors present an algorithm and complexity measure for parallel Fault Simulation as extended to the switch level. Using nine-valued logic, reverse level ordering, and the PHAFS, the switch level Fault Simulation complexity is reduced to O(L**2), where L is the number of levels of switches encountered when traversing from output to input. This computational complexity is far less than that of traditional methods, since it is polynomial with respect to the number of reverse levels in the circuit as opposed to the number of devices in the circuit. >
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Circuit partitioning for distributed VHDL Fault Simulation
Proceedings Ninth Annual IEEE International ASIC Conference and Exhibit, 1Co-Authors: C.a. RyanAbstract:Switch-level Faults, as opposed to traditional gate-level Faults can more accurately model physical failures found on an integrated circuit. However, one problem with switch-level Fault Simulation is that of long Simulation times. This paper addresses this problem by performing distributed switch-level Fault Simulation using a novel switch-level circuit partitioning technique. Transistor reverse level order circuit partitioning is shown to produce groups of transistors that share fan-in at nodes. Using this partitioning technique, results show that distributed switch-level Fault Simulation achieves increased speed-up over distributed switch-level Fault Simulation using random Fault set partitioning techniques.
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Compiled-code VHDL approximate Fault Simulation
Proceedings of Eighth International Application Specific Integrated Circuits Conference, 1Co-Authors: C.a. Ryan, Joseph G. TrontAbstract:Switch-level Faults, as opposed to traditional gate-level Faults, can more accurately model physical failures found in an integrated circuit. However, one problem with switch-level Fault Simulation is that of long Simulation times. This paper addresses this problem by performing fast approximate switch-level Fault Simulation using transistor reverse level ordering, and a novel 9-valued switch-level extension to observability. The probability of propagation of a Fault from an arbitrary line of the switch-level circuit to the primary output is shown to be a function of the average node fan-in and the line's distance to primary output. Using this probability, results show one order of magnitude of complexity speed-up as compared to traditional Fault Simulation techniques, while maintaining good accuracy.
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Multiple Fault Simulation with random and clustered Fault injection
Proceedings of Eighth International Application Specific Integrated Circuits Conference, 1Co-Authors: Charles E. Stroud, C.a. RyanAbstract:A logic and Fault simulator is described which provides gate-level multiple stuck-at Fault Simulation as well as traditional single stuck-at Fault Simulation. The multiple Fault Simulation supports random and clustered Fault injection for the verification and evaluation of multiple Fault detection capabilities of test vector sets as well as Fault and defect-tolerant design techniques.
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Bridging Fault Simulation using Iddq, logic, and delay testing
Conference Record AUTOTESTCON '95. 'Systems Readiness: Test Technology for the 21st Century', 1Co-Authors: C.a. RyanAbstract:Accepted integrated circuit verification techniques involve stuck-at Fault Simulation. However, it has been shown that the majority of actual physical Faults in the Faulty integrated circuit are bridging Faults. For this reason, the interest in bridging Fault Simulation techniques have increase. One characteristic with bridging Faults is that the bridging Fault may have electrical as well as logical behavior. This characteristic makes detection of bridging Faults more difficult and this characteristic increases the complexity of bridging Fault Simulation. The three techniques most widely used for bridging Fault Simulation are current testing, stuck-at testing, and delay testing. This paper compares the complexity and robustness of the three techniques and new developments in the three techniques. Results show the current testing technique to be the most robust and have the lowest complexity which approaches stuck-at Fault Simulation complexity.
I Pomeranz - One of the best experts on this subject based on the ideXlab platform.
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retro reintroducing tests for improved reverse order Fault Simulation
IEEE Transactions on Very Large Scale Integration Systems, 2020Co-Authors: I PomeranzAbstract:Reverse order Fault Simulation and its variations provide a test compaction option with a low computational effort that is applicable even when test constraints or complex Fault models preclude the application of other conventional test compaction procedures. This is the scenario considered in this brief. Reverse order Fault Simulation procedures remove unnecessary tests from a test set without otherwise modifying it. Reverse order Fault Simulation is typically applied once after the complete test set has been generated. This brief observes that when other test compaction procedures are not applied, forward-looking reverse order Fault Simulation sometimes yields a smaller test set if it is applied more often during the test generation process. However, applying it more often also increases the computational effort. This brief explains this phenomenon and describes a procedure that uses the new insights to improve the ability of forward-looking reverse order Fault Simulation to achieve test compaction at a reduced computational effort. The experimental results for benchmark circuits are presented to support the discussion.
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forward looking reverse order Fault Simulation for n detection test sets
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2009Co-Authors: I Pomeranz, S M ReddyAbstract:We extend the concept of forward-looking reverse order Fault Simulation to n-detection test sets. Forward-looking reverse order Fault Simulation is an efficient static test compaction process similar to reverse order Fault Simulation, but with the advantage that it results in test sets that do not contain any unnecessary tests. The application of test compaction procedures to n-detection test sets is important since the test sets are larger than conventional test sets. We demonstrate that forward-looking reverse order Fault Simulation produces smaller test sets than reverse order Fault Simulation and measure the quality of the resulting test sets by their bridging Fault coverage.
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Experimental results of forward-looking reverse order Fault Simulation on industrial circuits with scan
Proceedings 10th Asian Test Symposium, 2001Co-Authors: I Pomeranz, S M ReddyAbstract:Discusses an improved procedure named forward-looking Fault Simulation. The term forward-looking refers to the fact that certain tests are dropped because they are not necessary for detecting Faults that will be detected later in the Simulation process. The authors discuss an efficient implementation of forward-looking Fault Simulation in an industrial environment. They concentrate on reverse order Fault Simulation. Parallel pattern single Fault propagation (PPSFP) Simulation is used throughout the implementation of the forward-looking reverse order Fault Simulation process, since PPSFP is known to result in fast Fault Simulation for industrial circuits.
