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Ka Nang Leung - One of the best experts on this subject based on the ideXlab platform.

  • analysis of multistage amplifier Frequency Compensation
    IEEE Transactions on Circuits and Systems I-regular Papers, 2001
    Co-Authors: Ka Nang Leung
    Abstract:

    Frequency-Compensation techniques of single-, two- and three-stage amplifiers based on Miller pole splitting and pole-zero cancellation are re-analyzed. The assumptions made, transfer functions, stability criteria, bandwidths, and important design issues of most of the reported topologies are included. Several proposed methods to improve the published topologies are given. In addition, simulations and experimental results are provided to verify the analysis and to prove the effectiveness of the proposed methods.

  • ISCAS (5) - A novel Frequency Compensation technique for low-voltage low-dropout regulator
    ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349), 1999
    Co-Authors: Ka Nang Leung, Wing-hung Ki
    Abstract:

    A novel Frequency Compensation technique for low-voltage low-dropout regulator (LDR) is presented. The proposed technique, called pole-control Frequency Compensation (PCFC), provides faster loop response and does not require a large filtering capacitor. Both theoretical analysis and simulation show that the stability of the LDR using PCFC is independent of the load current, temperature and equivalent series resistance of the filtering capacitor. LDRs are well suited to portable equipment such as cellular phones, pagers and personal digital assistants.

  • ISCAS - Analysis on an alternative structure of damping-factor-control Frequency Compensation
    2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353), 1
    Co-Authors: Ka Nang Leung, Philip K. T. Mok, Johnny K. O. Sin
    Abstract:

    This paper introduces an alternative structure to implement damping-factor-control Frequency Compensation for three-stage amplifiers. A theoretical analysis is presented, and experimental results are included. From the experimental results, the new structure provides better phase margin and power supply rejection ratio but higher power consumption and larger chip area are required.

Mohammad Yavari - One of the best experts on this subject based on the ideXlab platform.

  • A fast settling on-chip low-dropout regulator with a robust Frequency Compensation scheme
    20th Iranian Conference on Electrical Engineering (ICEE2012), 2012
    Co-Authors: Mortaza Mojarad, Mohammad Yavari
    Abstract:

    An on-chip low-dropout (LDO) voltage regulator with a novel technique to improve the settling time and a robust Frequency Compensation scheme is presented in this paper. The total capacitance required for the utilized Compensation topology is only 2.8 pF. The proposed LDO regulator was implemented in a standard 0.35 µm CMOS technology and the simulation results show that the implemented LDO regulator operates from a supply voltage of 2 V to 4 V with a dropout voltage of 200 mV and the maximum load current of 120 mA, consuming 45 µA quiescent (ground) current.

  • ICECS - A novel Frequency Compensation scheme for on-chip low-dropout voltage regulators
    2011 18th IEEE International Conference on Electronics Circuits and Systems, 2011
    Co-Authors: Mortaza Mojarad, Mohammad Yavari
    Abstract:

    A new Frequency Compensation scheme for linear low-dropout (LDO) voltage regulators with on-chip applications is presented in this paper. The proposed Compensation technique uses a single capacitor of only 70 fF, making it suitable for system-on-chip (SoC) applications. The presented low-dropout regulator operates from a supply voltage of 1.8 V to 3 V with dropout voltage of 200 mV. The maximum output current of this LDO regulator is 100 mA with a quiescent current of 25 μA and it is simulated in a 0.35 μm CMOS technology.

  • ACTIVE-FEEDBACK SINGLE MILLER CAPACITOR Frequency Compensation TECHNIQUES FOR THREE-STAGE AMPLIFIERS
    Journal of Circuits Systems and Computers, 2010
    Co-Authors: Mohammad Yavari
    Abstract:

    This paper presents two novel active-feedback single Miller capacitor Frequency Compensation techniques for low-power three-stage amplifiers. These techniques include the active-feedback single Miller capacitor Frequency Compensation (AFSMC) and the dual active-feedback single Miller capacitor Frequency Compensation (DAFSMC). In the proposed techniques, only one Miller capacitor in series with a current buffer is utilized. The main advantages of the proposed three-stage amplifiers are the enhanced unity-gain bandwidth and the reduced silicon area. Small-signal analyses are performed and the design equations are obtained. Extensive HSPICE simulation results are provided to show the usefulness of the proposed AFSMC and DAFSMC amplifiers in both large and small capacitive loads.

Salvatore Pennisi - One of the best experts on this subject based on the ideXlab platform.

  • ICECS - High-performance Frequency Compensation topology for four-stage OTAs
    2014 21st IEEE International Conference on Electronics Circuits and Systems (ICECS), 2014
    Co-Authors: Alfio Dario Grasso, Salvatore Pennisi, Gaetano Palumbo, Giuseppe Di Cataldo
    Abstract:

    A power-efficient Frequency Compensation technique for four-stage transconductance amplifiers is proposed. Stability analysis and design equations are carried out based on the small-signal model. To verify the effectiveness of the Compensation scheme, a four-stage amplifier is designed in a standard CMOS 65-nm technology. The Compensation exploits passive components only and is implemented without entailing extra transistors, thus saving circuit complexity and power consumption. The amplifier achieves a 19-MHz gain-bandwidth product when driving a 1-nF capacitance by consuming only 80 μW from a 1-V supply. Simulation results show a significant improvement in both small-signal and large-signal amplifier performance with respect to prior art.

  • ISCAS - Constant and maximum bandwidth feedback amplifier with adaptive Frequency Compensation
    2012 IEEE International Symposium on Circuits and Systems, 2012
    Co-Authors: Salvatore Pennisi, Giuseppe Scotti, Alessandro Trifiletti
    Abstract:

    We demonstrated the feasibility of the adaptive Frequency Compensation approach to design maximum- and constant-bandwidth feedback amplifiers. A basic CMOS amplifier exhibiting 66-dB dc gain and 310-MHz gain-bandwidth product was designed. For closed-loop gains ranging from 1 to 10, the closed loop bandwidth was found never lower than 401 MHz. A similar amplifier with equal gain-bandwidth product, but adopting the traditional fixed Compensation approach, would exhibit a closed-loop bandwidth decreased to 33 MHz when the gain magnitude is set to 10. The enhanced Frequency performance is obtained with a 48% increase in current consumption, while the other main opamp performance parameters remain almost unchanged compared to the standard solution.

  • design methodology of miller Frequency Compensation with current buffer amplifier
    Iet Circuits Devices & Systems, 2008
    Co-Authors: W. Aloisi, G Palumbo, Salvatore Pennisi
    Abstract:

    Current buffers/amplifiers are used in series to the Miller Compensation capacitor with the aim of eliminating the positive zero introduced by the forward path. They are increasingly adopted because of their low-voltage features, high-speed performance and, recently, for their suitability to be used with large capacitive loads (when a current gain is introduced). The authors propose a novel and simple design approach for the Frequency Compensation of a two-stage amplifier exploiting a current buffer/amplifier. The procedure has been profitably applied to a class-AB two-stage CMOS operational transconductance amplifier, having a 100 pF load. In particular, three Compensation networks were designed using a 1.3 pF, 0.6 pF and 250 fF Compensation capacitor alternatively. Moreover, the adopted Compensation topology provides an improvement in terms of power supply rejection ratio, which was also analytically demonstrated. Simulations that are in very good agreement with theoretical results are also given.

  • Comparison of the Frequency Compensation Techniques for CMOS Two-Stage Miller OTAs
    IEEE Transactions on Circuits and Systems II: Express Briefs, 2008
    Co-Authors: Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi
    Abstract:

    Several design options are nowadays available for the Frequency Compensation of CMOS two-stage transconductance operational amplifiers, from the traditional Miller approach employing a nulling resistor or a voltage buffer, to a current buffer or the more modern current amplifier. However, designers have no results on the Frequency performance achievable that allow to consciously choose the best approach to meet the prescribed specifications efficiently. In this paper, a comparison among the possible Miller approaches is carried out by exploiting an analytical figure of merit that expresses a tradeoff between gain-bandwidth product, load capacitance, and total transconductance for a given value of phase margin. Interesting and useful results, even unexpected, are found. The accuracy of the comparison is also validated through simulations.

  • improved reversed nested miller Frequency Compensation technique with voltage buffer and resistor
    IEEE Transactions on Circuits and Systems Ii-express Briefs, 2007
    Co-Authors: Alfio Dario Grasso, G Palumbo, D Marano, Salvatore Pennisi
    Abstract:

    This brief introduces and develops a novel Frequency Compensation technique for three-stage operational transconductance amplifiers. The new Compensation topology exploits a voltage buffer and a nulling resistor to achieve a double pole-zero cancellation, occurring beyond the gain-bandwidth product. To verify the effectiveness of the Compensation scheme, an amplifier has been fabricated in a standard 0.5-mum CMOS process. Experimental measurements are found to be in good agreement with the theoretical analysis and show an improvement in small-signal and large-signal performances

Jose Silva-martinez - One of the best experts on this subject based on the ideXlab platform.

  • A Frequency Compensation scheme for LDO voltage regulators
    IEEE Transactions on Circuits and Systems I: Regular Papers, 2004
    Co-Authors: C.k. Chava, Jose Silva-martinez
    Abstract:

    A stable low dropout (LDO) voltage regulator topology for low equivalent series resistance (ESR) capacitive loads is presented. The proposed scheme generates a zero internally instead of relying on the zero generated by the load capacitor and its ESR combination for stability. It is demonstrated that this scheme realizes robust Frequency Compensation, facilitates the use of multilayer ceramic capacitors for the load of LDO regulators, and improves transient response and noise performance. Test results from a prototype fabricated in AMI 0.5-/spl mu/m CMOS technology provide the most important parameters of the regulator viz., ground current, load regulation, line regulation, output noise, and start-up time.

  • ISCAS (5) - A robust Frequency Compensation scheme for LDO regulators
    2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353), 1
    Co-Authors: C.k. Chava, Jose Silva-martinez
    Abstract:

    In the Frequency Compensation scheme of low drop out (LDO) voltage regulators, a zero generated by the series combination of load capacitor and its electro static resistance (ESR) plays an important role. This Frequency Compensation tends to be inefficient, as one has to take into consideration a range of specified values for load capacitor and R/sub ESR/, along with their variation with process and temperature. This paper presents a robust Frequency Compensation scheme that generates a zero internally without relying on RESR of load capacitor. The proposed Frequency Compensation has better RF noise rejection, low power consumption and improved transient response. The LDO regulator is designed in 0.35/spl mu/m TSMC technology.

Ismailyehea - One of the best experts on this subject based on the ideXlab platform.