The Experts below are selected from a list of 318 Experts worldwide ranked by ideXlab platform
Wenke Lee - One of the best experts on this subject based on the ideXlab platform.
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anomalous path detection with Hardware Support
Compilers Architecture and Synthesis for Embedded Systems, 2005Co-Authors: Tao Zhang, Xiaotong Zhuang, Santosh Pande, Wenke LeeAbstract:Embedded systems are being deployed as a part of critical infrastructures and are vulnerable to malicious attacks due to internet accessibility. Intrusion detection systems have been proposed to protect computer systems from unauthorized penetration. Detecting an attack early on pays off since further damage is avoided and in some cases, resilient recovery could be adopted. This is especially important for embedded systems deployed in critical infrastructures such as Power Grids etc. where a timely intervention could save catastrophes. An intrusion detection system monitors dynamic program behavior against normal program behavior and raises an alert when an anomaly is detected. The normal behavior is learnt by the system through training and profiling.However, all current intrusion detection systems are purely software based and thus suffer from large performance degradation due to constant monitoring operations inserted in application code. Due to the potential performance overheads, software based solutions cannot monitor program behavior at a very fine level of granularity, thus leaving potential security holes as shown in the literature. Another important drawback of such methods is that they are unable to detect intrusions in near real time and the time lag could prove disastrous in real time embedded systems. In this paper, we propose a Hardware-based approach to verify program execution paths of target applications dynamically and to detect anomalous executions. With Hardware Support, our approach offers multiple advantages over software based solutions including minor performance degradation, much stronger detection capability (a larger variety of attacks get detected) and zero-latency reaction upon an anomaly for near real time detection and thus much better security.
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CASES - Anomalous path detection with Hardware Support
Proceedings of the 2005 international conference on Compilers architectures and synthesis for embedded systems - CASES '05, 2005Co-Authors: Tao Zhang, Xiaotong Zhuang, Santosh Pande, Wenke LeeAbstract:Embedded systems are being deployed as a part of critical infrastructures and are vulnerable to malicious attacks due to internet accessibility. Intrusion detection systems have been proposed to protect computer systems from unauthorized penetration. Detecting an attack early on pays off since further damage is avoided and in some cases, resilient recovery could be adopted. This is especially important for embedded systems deployed in critical infrastructures such as Power Grids etc. where a timely intervention could save catastrophes. An intrusion detection system monitors dynamic program behavior against normal program behavior and raises an alert when an anomaly is detected. The normal behavior is learnt by the system through training and profiling.However, all current intrusion detection systems are purely software based and thus suffer from large performance degradation due to constant monitoring operations inserted in application code. Due to the potential performance overheads, software based solutions cannot monitor program behavior at a very fine level of granularity, thus leaving potential security holes as shown in the literature. Another important drawback of such methods is that they are unable to detect intrusions in near real time and the time lag could prove disastrous in real time embedded systems. In this paper, we propose a Hardware-based approach to verify program execution paths of target applications dynamically and to detect anomalous executions. With Hardware Support, our approach offers multiple advantages over software based solutions including minor performance degradation, much stronger detection capability (a larger variety of attacks get detected) and zero-latency reaction upon an anomaly for near real time detection and thus much better security.
Cem Yuksel - One of the best experts on this subject based on the ideXlab platform.
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Patch Textures: Hardware Support for Mesh Colors.
IEEE transactions on visualization and computer graphics, 2020Co-Authors: Ian Mallett, Larry Seiler, Cem YukselAbstract:Mesh colors provide an effective alternative to standard texture mapping. They significantly simplify the asset production pipeline by removing the need for defining a mapping and eliminate rendering artifacts due to seams. This paper addresses the problem that using mesh colors for real-time rendering has not been practical, due to the absence of Hardware Support. We show that it is possible to provide full Hardware texture filtering Support for mesh colors with minimal changes to existing GPUs by introducing a Hardware-friendly representation for mesh colors that we call patch textures, which can have quadrilateral or triangular topology. We discuss the Hardware modifications needed for storing and filtering patch textures, including anisotropic filtering. This paper extends our previous work by discussing and comparing patch edge-handling approaches, including an option for sampling the textures of neighboring patches using an adjacency map. We also provide extensive discussions regarding data duplication, a partial implementation present in existing Hardware, and the difficulties with providing a similar Hardware Support for Ptex.
Emil Jovanov - One of the best experts on this subject based on the ideXlab platform.
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Hardware Support for code integrity in embedded processors
Compilers Architecture and Synthesis for Embedded Systems, 2005Co-Authors: Milena Milenkovic, Aleksandar Milenkovic, Emil JovanovAbstract:Computer security becomes increasingly important with continual growth of the number of interconnected computing platforms. Moreover, as capabilities of embedded processors increase, the applications running on these systems also grow in size and complexity, and so does the number of security vulnerabilities. Attacks that impair code integrity by injecting and executing malicious code are one of the major security issues. This problem can be addressed at different levels, from more secure software and operating systems, down to solutions that require Hardware Support. Most of the existing techniques tackle the problem of security flaws at the software level, but this approach lacks generality and often induces prohibitive overhead in performance and cost, or generates a significant number of false alarms. On the other hand, a further increase in the number of transistors on a single chip enables integrated Hardware Support for functions that formerly were restricted to the software domain. Hardware-Supported defense techniques have the potential to be more general and more efficient than solely software solutions. This paper proposes four new architectural extensions to ensure complete run-time code integrity using instruction block signature verification. The experimental analysis shows that the proposed techniques have low performance and energy overhead. In addition, the proposed mechanism has low Hardware complexity, and does not impose either changes to the compiler or changes to the existing instruction set architecture.
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CASES - Hardware Support for code integrity in embedded processors
Proceedings of the 2005 international conference on Compilers architectures and synthesis for embedded systems - CASES '05, 2005Co-Authors: Milena Milenkovic, Aleksandar Milenkovic, Emil JovanovAbstract:Computer security becomes increasingly important with continual growth of the number of interconnected computing platforms. Moreover, as capabilities of embedded processors increase, the applications running on these systems also grow in size and complexity, and so does the number of security vulnerabilities. Attacks that impair code integrity by injecting and executing malicious code are one of the major security issues. This problem can be addressed at different levels, from more secure software and operating systems, down to solutions that require Hardware Support. Most of the existing techniques tackle the problem of security flaws at the software level, but this approach lacks generality and often induces prohibitive overhead in performance and cost, or generates a significant number of false alarms. On the other hand, a further increase in the number of transistors on a single chip enables integrated Hardware Support for functions that formerly were restricted to the software domain. Hardware-Supported defense techniques have the potential to be more general and more efficient than solely software solutions. This paper proposes four new architectural extensions to ensure complete run-time code integrity using instruction block signature verification. The experimental analysis shows that the proposed techniques have low performance and energy overhead. In addition, the proposed mechanism has low Hardware complexity, and does not impose either changes to the compiler or changes to the existing instruction set architecture.
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Acceleration of nonnumeric operations using Hardware Support for the Ordered Table Hashing algorithms
IEEE Transactions on Computers, 2002Co-Authors: Emil Jovanov, Veljko Milutinovic, A.r. HursonAbstract:The paper introduces a new approach to acceleration of nonnumeric, database, and information retrieval operations. While traditional techniques accelerate the most time-critical high-level software constructs, we propose novel low-level primitives and demonstrate how these primitives improve database operations. Radix sorting, hashing, and bit-vector operations are used to develop a new class of nonnumeric algorithms - OTHER (Ordered Table Hashing and Radix sort algorithms) - based on low-level hashing operations Init, Mark, and Scan. We have proposed and evaluated two Hardware accelerators for OTHER algorithms. It is shown that a low complexity Hardware Support (less than 10 K transistors) can significantly improve the performance of nonnumeric operations.
Paul Chow - One of the best experts on this subject based on the ideXlab platform.
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Benefits of Adding Hardware Support for Broadcast and Reduce Operations in MPSoC Applications
ACM Transactions on Reconfigurable Technology and Systems, 2014Co-Authors: Yuanxi Peng, Manuel Saldana, Christopher A. Madill, Xiaofeng Zou, Paul ChowAbstract:MPI has been used as a parallel programming model for supercomputers and clusters and recently in MultiProcessor Systems-on-Chip (MPSoC). One component of MPI is collective communication and its performance is key for certain parallel applications to achieve good speedups. Previous work showed that, with synthetic communication-only benchmarks, communication improvements of up to 11.4-fold and 22-fold for broadcast and reduce operations, respectively, can be achieved by providing Hardware Support at the network level in a Network-on-Chip (NoC). However, these numbers do not provide a good estimation of the advantage for actual applications, as there are other factors that affect performance besides communications, such as computation. To this end, we extend our previous work by evaluating the impact of Hardware Support over a set of five parallel application kernels of varying computation-to-communication ratios. By introducing some useful computation to the performance evaluation, we obtain more representative results of the benefits of adding Hardware Support for broadcast and reduce operations. The experiments show that applications with lower computation-to-communication ratios benefit the most from Hardware Support as they highly depend on efficient collective communications to achieve better scalability. We also extend our work by doing more analysis on clock frequency, resource usage, power, and energy. The results show reasonable scalability for resource utilization and power in the network interfaces as the number of channels increases and that, even though more power is dissipated in the network interfaces due to the added Hardware, the total energy used can still be less if the actual speedup is sufficient. The application kernels are executed in a 24-embedded-processor system distributed across four FPGAs.
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FPL - Hardware Support for Broadcast and Reduce in MPSoC
2011 21st International Conference on Field Programmable Logic and Applications, 2011Co-Authors: Yuanxi Peng, Manuel Saldana, Paul ChowAbstract:MPI has been used as a parallel programming model for supercomputers and clusters but also in Multiprocessor System-on-Chip. One component of MPI is collective communication and its performance is key for parallel applications to achieve good speedups. Considerable research has been done to optimize such communication by improving the MPI library algorithms. However, these optimizations are focused on the processing nodes (end-points in a network) rather than on the network itself. In this paper, we target a Network-on-Chip (NoC) and modify it to provide Hardware Support for broadcast and reduce operations for the ArchES-MPI library. This library is a subset implementation of the MPI standard targeting embedded processors and Hardware accelerators implemented in FPGAs. The experimental results show that for a system with 24 embedded processors, the broadcast and reduce operations improved up to 11.4-fold and 22-fold, respectively. Higher benefits are expected for larger systems at the expense of a modest increase resource utilization.
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Hardware Support for prescient instruction prefetch
High-Performance Computer Architecture, 2004Co-Authors: Tor M Aamodt, Paul Chow, Per Hammarlund, Hong Wang, John ShenAbstract:This paper proposes and evaluates Hardware mechanisms for Supporting prescient instruction prefetch — an approach to improving single-threaded application performance by using helper threads to perform instruction prefetch. We demonstrate the need for enabling store-to-load communication and selective instruction execution when directly pre-executing future regions of an application that suffer I-cache misses. Two novel Hardware mechanisms, safe-store and YAT-bits, are introduced that help satisfy these requirements. This paper also proposes and evaluates .nite state machine recall, a technique for limiting pre-execution to branches that are hard to predict by leveraging a counted I-prefetch mechanism. On a research Itanium®SMT processor with next line and streaming I-prefetch mechanisms that incurs latencies representative of next generation processors, prescient instruction prefetch can improve performance by an average of 10.0% to 22% on a set of SPEC 2000 benchmarks that suffer significant I-cache misses. Prescient instruction prefetch is found to be competitive against even the most aggressive research Hardware instruction prefetch technique: fetch directed instruction prefetch.
Darshika G. Perera - One of the best experts on this subject based on the ideXlab platform.
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Analysis of single-chip Hardware Support for mobile and embedded applications
2013 IEEE Pacific Rim Conference on Communications Computers and Signal Processing (PACRIM), 2013Co-Authors: Darshika G. PereraAbstract:As mobile and handheld devices are gaining popularity, many applications have found their ways into these devices. In order to use these mobile systems effectively and efficiently, it is important to optimize their embedded software and Hardware. This work focuses on Hardware Support for mobile and embedded applications in single-chip format so as to reduce the Hardware footprint as required in these handheld devices. Applications specific circuits, single-core microprocessor, and field programmable gate arrays are presented, and their strengths and weaknesses are discussed. Reconfigurable computing systems, specifically FPGA-based approaches, are introduced, and techniques for their reconfiguration are analyzed. It is concluded that reconfigurable FPGA-based system is currently the best option to deliver embedded applications that have stringent requirements.
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On-Chip Hardware Support for Similarity Measures
2007 IEEE Pacific Rim Conference on Communications Computers and Signal Processing, 2007Co-Authors: Darshika G. PereraAbstract:In Web mining applications, an enormous amount of data needs to be processed quickly and efficiently. Thus, Hardware Support is crucial to enhance the performance of these operations. We are investigating on-chip Hardware Support for web mining operations. In this work, we introduce chip level Hardware Support for similarity measure computation. We have implemented both the software and Hardware versions of various similarity measures using a hierarchical platform-based design approach to facilitate component reuse at different levels of abstraction. Software modules are executed on a reconfigurable soft processor core on the same field programmable gate array (FPGA) as the Hardware implementations for performance comparison purpose. Our experimental results show that the performance of web mining operations could be significantly enhanced by using on-chip Hardware.
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AINA Workshops (1) - An Investigation of Chip-Level Hardware Support for Web Mining
21st International Conference on Advanced Information Networking and Applications Workshops (AINAW'07), 2007Co-Authors: Darshika G. PereraAbstract:In this work, we investigate the use of Hardware at the chip level to Support some fundamental Web mining operations. Both software and Hardware versions of the same operators are implemented on field programmable gate arrays (FPGAs). The software versions are executed on a soft IP core on the same FPGA chip as the Hardware implementation, ensuring their fair performance comparison. The Hardware operators are structured hierarchically following the bottom-up and platform-based design strategies. These design approaches provide the opportunity to measure the performance of the respective Hardware and software operators at various levels of abstraction. Our proof of concept investigation has shown that with the proper system-level design strategies, there is a tremendous potential in Hardware Support at the chip level for information retrieval and Web mining operations.
