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Yong-seo Koo - One of the best experts on this subject based on the ideXlab platform.

  • A Novel Low Dynamic Resistance Dual-Directional SCR With High Holding Voltage for 12 V Applications
    IEEE Journal of the Electron Devices Society, 2020
    Co-Authors: Yong-seo Koo
    Abstract:

    The excellent area efficiency of dual-directional SCRs (DDSCRs) have made them desirable for low-Voltage and high-Voltage applications. However, to implement the required symmetrical structure, conventional DDSCRs have to lengthen their ESD discharge path. In addition, the low Holding Voltage of existing DDSCRs is not suitable for high-Voltage applications. In this study, a novel DDSCR with a high Holding Voltage and low dynamic resistance is proposed and its electrical characteristics are verified. The proposed DDSCR has two additional internal parasitic bipolar transistors compared to a conventional low- triggering Voltage DDSCR (LTDDSCR). Self-gate biasing reduces latch-mode feedback between the parasitic bipolar transistors in the SCR. The device is fabricated using 0.13 $\mu {\mathrm{ m}}$ BCD processes and implements a segment layout resulting in a very low dynamic resistance of $2.2~{\Omega }$ and excellent Holding Voltages of up to 17.2 V. The proposed DDSCR demonstrates improved reliability and area efficiency for 12 V applications.

  • A Gate-Grounded NMOS-Based Dual-Directional ESD Protection With High Holding Voltage for 12V Application
    IEEE Transactions on Device and Materials Reliability, 2020
    Co-Authors: Bo Bae Song, Yong-seo Koo
    Abstract:

    Dual-direction electrostatic discharge (ESD) protection devices can discharge both positive and negative ESD surges, owing to their excellent area efficiency. This study proposes a novel dual-direction MOSFET ESD protection device with a high Holding Voltage. Most existing dual-direction ESD protection devices are based on silicon-controlled rectifiers (SCR). Among them, the low triggering dual-directional SCR (LTDDSCR) has good trigger characteristics, but with low Holding Voltage. In contrast, the proposed high-Holding-Voltage dual-direction NMOS (HHDDNMOS) operates using two NPN parasitic bipolar transistors connected to the ESD discharge path and has a very high Holding Voltage and excellent snapback characteristics. The electrical and dual-directional characteristics of HHDDNMOS were analyzed using the transmission-line -pulsing system, and the latch-up immunity was verified by conducting transient-induced latch-up tests using the 0.18- $\mu \text{m}$ BCD process.

  • A Novel Dual-Directional SCR Structure With High Holding Voltage for 12-V Applications in 0.13-μm BCD Process
    IEEE Transactions on Electron Devices, 2020
    Co-Authors: Bo Bae Song, Yong-seo Koo
    Abstract:

    This article proposes a dual-directional silicon-controlled rectifier (SCR) with a novel structure and high Holding Voltage to improve the electrostatic discharge (ESD) design area efficiency in high-Voltage environments. In terms of structure, by decreasing the emitter injection efficiency of the p-n-p parasitic bipolar transistor formed at the bottom of the gate region, the SCR positive feedback gain is reduced, which endows the proposed device with improved snapback characteristics compared with the conventional low-Voltage triggering SCR (LVTSCR) and low-trigger dual directional SCR (LTDDSCR). This article conducted 2-D and mixed-mode simulations to compare and analyze the operating principles of the proposed and traditional devices. Additionally, experimental devices were fabricated under the same conditions using the 0.13- $\mu \text{m}$ process to verify their electrical properties and latch-up immunity by measuring the transmission line pulse (TLP) and transient latch-up (TLU). This article also conducted a detailed analysis on the optimization of electrical properties for the ESD design window of the proposed device according to the design variables and application of segment topology, and also analyzed the temperature reliability using a hot chuck control system. The measurement results reveal that the proposed device is highly suitable for the 12-V-class ESD design window, has improved reliability, and can provide excellent area efficiency in related applications.

  • A New SCR Structure With High Holding Voltage and Low ON-Resistance for 5-V Applications
    IEEE Transactions on Electron Devices, 2020
    Co-Authors: Yong-seo Koo
    Abstract:

    This article proposes a new silicon-controlled rectifier (SCR)-based electrostatic discharge (ESD) protection device suitable for 5-V applications. The proposed ESD protection device has an additional n-p-n parasitic bipolar transistor that provides an extremely short ESD discharge path. Compared with the conventional Low-Voltage-Trigger SCR (LVTSCR) and Low-Ron SCR (LRSCR), it has excellent ON-resistance and improved reverse characteristics. Furthermore, it has structurally enhanced trigger Voltage and Holding Voltage characteristics. A conventional LVTSCR, LRSCR, and the proposed ESD protection device were fabricated with the same width using a 0.18- $\mu \text{m}$ bipolar CMOS DMOS (BCD) process to verify the improvement in electrical characteristics and current driving capability of the new device. Transmission line pulsing (TLP) and a hot chuck control system were used to measure and compare the latch-up, electrical characteristics, and temperature reliability of the three devices. The measurements demonstrate that the proposed ESD protection device provides improved reliability and higher area efficiency for 5 V or similar applications.

  • Design of 4H-SiC-Based Silicon-Controlled Rectifier With High Holding Voltage Using Segment Topology for High-Voltage ESD Protection
    IEEE Electron Device Letters, 2020
    Co-Authors: Byung-seok Lee, Sang Gi Kim, Yong-seo Koo
    Abstract:

    In this letter, a new silicon-controlled rectifier (SCR) structure fabricated using 4H-SiC materials has been proposed and investigated. The proposed structure alleviates the strong-snapback phenomenon that occurs in the 4H-SiC SCR and demonstrates low trigger Voltage and high Holding Voltage characteristics. The proposed device exhibits improved snapback characteristics with very high Holding Voltage against electrostatic discharge surges owing to the structural features and application of segment topology. It also has excellent on-resistance and improved thermal reliability owing to the physical characteristics of 4H-SiC. Traditional SCR and low-Voltage trigger SCR (LVTSCR) are fabricated with 4H-SiC under the same conditions and their electrical characteristics are comparatively analyzed with those of the proposed SCR. This study also evaluates the electrical characteristics at high temperatures (300–500 K) to verify the high- temperature reliability of the proposed structure.

Ming-dou Ker - One of the best experts on this subject based on the ideXlab platform.

  • Transient Voltage Suppressor (TVS) on Signal Integrity of Microelectronics System with CMOS ICs under System-Level ESD Test
    2020 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), 2020
    Co-Authors: Yu-shu Shen, Ming-dou Ker, Hsin-chin Jiang
    Abstract:

    Transient Voltage suppressor (TVS) has been widely used on the PCB to protect the microelectronics system against the system-level electrostatic discharge (ESD) events. However, the signal integrity of the system operations may be destroyed after the system-level ESD test, if the TVS was designed with a Holding Voltage lower than the operating Voltage of CMOS ICs those equipped in the system. In this work, the signal integrity of microelectronics system protected by the TVS with different Holding Voltages was studied under the system-level ESD test. By monitoring the transient Voltage waveforms in the time domain during system-level ESD test, the system malfunction has been found when the TVS is with a lower Holding Voltage. Therefore, the Holding Voltage of TVS must be greater than the system operating Voltage to keep the well signal integrity in the applications.

  • Comparison Between High-Holding-Voltage SCR and Stacked Low-Voltage Devices for ESD Protection in High-Voltage Applications
    IEEE Transactions on Electron Devices, 2018
    Co-Authors: Chia-tsen Dai, Ming-dou Ker
    Abstract:

    The modified silicon-controlled rectifier (SCR) fabricated in a 0.25- $\mu \text{m}$ high-Voltage (HV) bipolar-CMOS-DMOS (BCD) technology has been proposed to seek for both effective electrostatic discharge (ESD) protection and latchup immunity. Experimental results show that one of the proposed SCRs has a high Holding Voltage of up to ~30 V in the 100-ns transmission line pulsing measurement results. However, through the experimental verification by using the transient latchup test, the Holding Voltage of such proposed device decreases to ~20 V. It is due to the increased bipolar junction transistor current gains of the SCR path induced by the Joule-heating effect in the long-term measurement. For 20-V circuit applications, the ESD robustness of the proposed SCR with a Holding Voltage of ~20 V is lower than that of stacked low-Voltage p-type MOS in the previous studies. Developing special modification of such HV devices is inefficient to achieve both effective ESD protection and latchup-free design in this 0.25- $\mu \text{m}$ HV BCD technology.

  • ESD Protection Design With Stacked High-Holding-Voltage SCR for High-Voltage Pins in a Battery-Monitoring IC
    IEEE Transactions on Electron Devices, 2016
    Co-Authors: Chia-tsen Dai, Ming-dou Ker
    Abstract:

    For high-Voltage (HV) applications, the electrostatic discharge (ESD) protection design using a traditional HV device, such as laterally diffused MOSFETs, usually consumes large silicon area to meet sufficient ESD specification. In this paper, an area-efficient ESD protection design with stacked high-Holding-Voltage silicon-controlled rectifier (HHVSCR) is proposed and verified in a 0.25- $\mu \text{m}$ 5/60 V Bipolar-CMOS-DMOS process. The proposed HHVSCR is fabricated in low-Voltage wells and has the characteristics of HHV and high failure current with the same silicon area as the traditional SCR. From the experimental results, the proposed HHVSCR stacking structure can fit the desired ESD protection design window for the 60 V pins of a battery-monitoring IC and successfully protect these 60 V pins against 7-kV human-body-mode ESD stress.

  • pmos based power rail esd clamp circuit with adjustable Holding Voltage controlled by esd detection circuit
    Electrical Overstress Electrostatic Discharge Symposium, 2011
    Co-Authors: Chihting Yeh, Yungchih Liang, Ming-dou Ker
    Abstract:

    A new power-rail ESD clamp circuit designed with PMOS as main ESD clamp device has been proposed and verified in a 65nm 1.2V CMOS process. The new proposed design with adjustable Holding Voltage controlled by the ESD detection circuit has better immunity against mis-trigger or transient-induced latch-on event. The layout area and the standby leakage current of this new proposed design are much superior to that of traditional RC-based power-rail ESD clamp circuit with NMOS as main ESD clamp device.

  • design of power rail esd clamp circuit with adjustable Holding Voltage against mis trigger or transient induced latch on events
    International Symposium on Circuits and Systems, 2011
    Co-Authors: Chihting Yeh, Yungchih Liang, Ming-dou Ker
    Abstract:

    In this work, a new design of the ESD-transient detection circuit with the n-channel metal-oxide-semiconductor (nMOS) transistor drawn in the layout style of big field-effect transistor (BigFET) has been proposed and verified in a 65nm 1.2V CMOS process. As compared to the traditional RC-based ESD-transient detection circuit, the layout area of the new ESD-transient detection circuit can be greatly reduced by more than 54%. From the experimental results, the new proposed ESD-transient detection circuit with adjustable Holding Voltage can achieve long turn-on duration under the ESD stress condition, as well as better immunity against mis-trigger or transient-induced latch-on event under the fast power-on and transient noise conditions.

Juin J. Liou - One of the best experts on this subject based on the ideXlab platform.

Yan Han - One of the best experts on this subject based on the ideXlab platform.

  • Design and Analysis of an Area-Efficient High Holding Voltage ESD Protection Device
    IEEE Transactions on Electron Devices, 2015
    Co-Authors: Jie Zeng, Shurong Dong, Yan Han, J J Liou, Lei Zhong, Weihuai Wang
    Abstract:

    A novel electrostatic discharge protection device gate-grounded nMOS (GGnMOS) incorporated silicon-controlled rectifier (GGISCR) is proposed in this paper. With a distinguished feature of an imbedded floating P+ region, the GGISCR is demonstrated to be superior to the conventional low Voltage triggered SCR and GGnMOS in terms of high area efficiency and high Holding Voltage. The operational mechanism of GGISCR device is discussed in detail, and the effect of floating P+ region on the GGISCR’s $I$ – $V$ characteristics is analyzed via TCAD simulation results as well.

  • High Holding Voltage SCR-LDMOS Stacking Structure With Ring-Resistance-Triggered Technique
    IEEE Electron Device Letters, 2013
    Co-Authors: Bin Zhang, Shurong Dong, Yan Han, Jianfeng Zheng, Bo Song, Hailian Liang
    Abstract:

    A novel ring-resistance-triggered stacked SCR-laterally diffused MOSs has been successfully verified in a 0.35 μm, 30-V/5-V bipolar CMOS DMOS process to solve the coupling of trigger Voltage and Holding Voltage in stacking structures. The Holding Voltage of the proposed structure can be modulated by varying stacking numbers, and a high Holding Voltage of 22 V has been achieved using six stacks. On the other side, the trigger Voltage almost keeps constant at ~ 53 V and a high failure current of 3.5 A has been achieved.

  • high Holding Voltage silicon controlled rectifier for esd applications
    IEEE Electron Device Letters, 2012
    Co-Authors: Shurong Dong, Meng Miao, Jie Zeng, Yan Han
    Abstract:

    Low-Voltage-triggering silicon-controlled rectifier (LVTSCR) having a gate structure can offer a low trigger Voltage in electrostatic discharge (ESD) applications. To avoid the threat of latch-up, the lateral width of LVTSCR is often stretched to obtain a relatively high Holding Voltage. The resulting lateral dimension increase, however, enlarges the size of LVTSCR. In this letter, a new method to increase the Holding Voltage of LVTSCR is developed. It is based on adding a floating-n-well region in the LVTSCR and can increase the Holding Voltage without requiring additional layout area. Furthermore, with this new LVTSCR, it is possible to implement an ESD protection operation within a very small window of 1 V.

  • Lateral IGBT in thin SOI process for high Voltage ESD application
    2012 IEEE International Conference on Electron Devices and Solid State Circuit (EDSSC), 2012
    Co-Authors: Shurong Dong, Jie Zeng, Yan Han, Jianfeng Zheng
    Abstract:

    A high Voltage laterally insulated-gate-bipolar-transistor (LIGBT) built in ultra-thin silicon-on-insulator (SOI) is reported. A theoretical analysis about the efficient approach to increasing the Holding Voltage of LIGBT starting with BJT's has been proposed. Higher Holding Voltage and almost the same turn-on speed is achieved by segmenting the emitter area of LIGBT to increase the resistance.

  • Silicon-Controlled Rectifier Stacking Structure for High-Voltage ESD Protection Applications
    IEEE Electron Device Letters, 2010
    Co-Authors: Zhiwei Liu, Juin J. Liou, Shurong Dong, Yan Han
    Abstract:

    Latchup immunity is a challenging issue for the design of power supply clamps used in high-Voltage electrostatic discharge (ESD) protection applications. While silicon-controlled rectifiers (SCRs) are highly robust ESD devices, they are traditionally not suited for high-Voltage ESD due to their inherent low Holding Voltage and, thus, vulnerability to latchup. In this letter, a novel SCR stacking structure with an extremely high Holding Voltage, very small snapback, and acceptable failure current has been developed. The new and existing high Holding Voltage ESD devices are also compared to demonstrate the advancement of this work.

Shurong Dong - One of the best experts on this subject based on the ideXlab platform.

  • An improved GGNMOS triggered SCR for high Holding Voltage ESD protection applications
    Chinese Physics B, 2015
    Co-Authors: Shuai Zhang, Shurong Dong, Jie Zeng, Lei Zhong
    Abstract:

    Developing an electrostatic discharge (ESD) protection device with a better latch-up immunity has been a challenging issue for the nanometer complementary metal-oxide semiconductor (CMOS) technology. In this work, an improved grounded-gate N-channel metal-oxide semiconductor (GGNMOS) transistor triggered silicon-controlled rectifier (SCR) structure, named GGSCR, is proposed for high Holding Voltage ESD protection applications. The GGSCR demonstrates a double snapback behavior as a result of progressive trigger-on of the GGNMOS and SCR. The double snapback makes the Holding Voltage increase from 3.43 V to 6.25 V as compared with the conventional low-Voltage SCR. The TCAD simulations are carried out to verify the modes of operation of the device.

  • Design and Analysis of an Area-Efficient High Holding Voltage ESD Protection Device
    IEEE Transactions on Electron Devices, 2015
    Co-Authors: Jie Zeng, Shurong Dong, Yan Han, J J Liou, Lei Zhong, Weihuai Wang
    Abstract:

    A novel electrostatic discharge protection device gate-grounded nMOS (GGnMOS) incorporated silicon-controlled rectifier (GGISCR) is proposed in this paper. With a distinguished feature of an imbedded floating P+ region, the GGISCR is demonstrated to be superior to the conventional low Voltage triggered SCR and GGnMOS in terms of high area efficiency and high Holding Voltage. The operational mechanism of GGISCR device is discussed in detail, and the effect of floating P+ region on the GGISCR’s $I$ – $V$ characteristics is analyzed via TCAD simulation results as well.

  • High Holding Voltage SCR-LDMOS Stacking Structure With Ring-Resistance-Triggered Technique
    IEEE Electron Device Letters, 2013
    Co-Authors: Bin Zhang, Shurong Dong, Yan Han, Jianfeng Zheng, Bo Song, Hailian Liang
    Abstract:

    A novel ring-resistance-triggered stacked SCR-laterally diffused MOSs has been successfully verified in a 0.35 μm, 30-V/5-V bipolar CMOS DMOS process to solve the coupling of trigger Voltage and Holding Voltage in stacking structures. The Holding Voltage of the proposed structure can be modulated by varying stacking numbers, and a high Holding Voltage of 22 V has been achieved using six stacks. On the other side, the trigger Voltage almost keeps constant at ~ 53 V and a high failure current of 3.5 A has been achieved.

  • high Holding Voltage silicon controlled rectifier for esd applications
    IEEE Electron Device Letters, 2012
    Co-Authors: Shurong Dong, Meng Miao, Jie Zeng, Yan Han
    Abstract:

    Low-Voltage-triggering silicon-controlled rectifier (LVTSCR) having a gate structure can offer a low trigger Voltage in electrostatic discharge (ESD) applications. To avoid the threat of latch-up, the lateral width of LVTSCR is often stretched to obtain a relatively high Holding Voltage. The resulting lateral dimension increase, however, enlarges the size of LVTSCR. In this letter, a new method to increase the Holding Voltage of LVTSCR is developed. It is based on adding a floating-n-well region in the LVTSCR and can increase the Holding Voltage without requiring additional layout area. Furthermore, with this new LVTSCR, it is possible to implement an ESD protection operation within a very small window of 1 V.

  • Lateral IGBT in thin SOI process for high Voltage ESD application
    2012 IEEE International Conference on Electron Devices and Solid State Circuit (EDSSC), 2012
    Co-Authors: Shurong Dong, Jie Zeng, Yan Han, Jianfeng Zheng
    Abstract:

    A high Voltage laterally insulated-gate-bipolar-transistor (LIGBT) built in ultra-thin silicon-on-insulator (SOI) is reported. A theoretical analysis about the efficient approach to increasing the Holding Voltage of LIGBT starting with BJT's has been proposed. Higher Holding Voltage and almost the same turn-on speed is achieved by segmenting the emitter area of LIGBT to increase the resistance.