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Sidlgata V. Sreenivasan - One of the best experts on this subject based on the ideXlab platform.
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Status of UV Imprint Lithography for Nanoscale Manufacturing
Comprehensive Nanoscience and Technology, 2020Co-Authors: Tejinder Singh, Sidlgata V. Sreenivasan, J. Choi, P. Schumaker, Frank Y. XuAbstract:For over a decade, Imprint Lithography literature has touted the remarkable sub-10 nm resolution and the promise of low-cost, large-area nanoscale manufacturing. However, there has been legitimate skepticism from the device community about the viability of Imprint Lithography in manufacturing because of a lack of comprehensive development in areas such as long-range order, overlay, low defectivity, mask life, and high throughput. In recent years, it has become evident that Imprint Lithography is maturing in its manufacturing attributes not only due to development in basic technology and the infrastructure around it but also due to application drivers, specifically high-density data storage including patterned magnetic media and solid-state memory. These early applications are likely to lead to additional high-impact applications of Imprint Lithography in several other sectors. Here, a status of ultraviolet (UV) Imprint Lithography technology is provided with a specific focus on its applicability to high-volume manufacturing of nanoscale devices.
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PARTIALLY CONSTRAINED COMPLIANT STAGES FOR HIGH RESOLUTION Imprint Lithography
2020Co-Authors: B. J. Choi, Sidlgata V. Sreenivasan, S. Johnson, Matthew E Colburn, Todd BaileyAbstract:This paper presents design of partially constrained compliant stages for high-resolution (sub 100 nm) Imprint Lithography machines. The kinematic designs of the stages allow passive alignment of two flat surfaces and enable shear-free separation. This stage is a critical component in a new Lithography process known as Step and Flash Imprint Lithography (SFIL). The orientation stage requirements are distinct from those used in traditional photoLithography since the depth of focus of projection optics allows for larger errors in the alignment process. Experiments have been performed to demonstrate sub 100nm Imprints on silicon substrates.
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Step and Flash Imprint Lithography: A Technology Review
2020Co-Authors: Todd Bailey, John G. Ekerdt, Sidlgata V. Sreenivasan, Matthew E Colburn, Byung Jin Choi, Annette C. Grot, Mario J. Meissl, Michael D. Stewart, Carlton G WillsonAbstract:The development of Imprint Lithography is an attempt by researchers to meet or exceed the size targets outlined in the SIA roadmap for semiconductors, while circumventing the expensive exposure sources and optics required by more conventional next generation lithographies, such as extreme UV, electron projection, and X-ray lithographies. There are promising applications in addition to the semiconductor arena, such as micro-electromechanical devices (MEMs), micro-optics, and patterned storage media. Imprint Lithography has the advantage that it uses fundamental fluid displacement principles to define a pattern, rather than i mage reduction with diffraction corrections, but the temperatures required by the more traditional micromolding or hot embossing techniques may present insurmountable obstacles in overlay alignment accuracy, and for applications requiring high throughput. Step and Flash Imprint Lithography (SFIL), being developed primarily at the University of Texas at Austin, overcomes these issues by using a rigid, UV-transparent Imprint template, and a bilayer resist scheme composed of an organic planarizing layer and a low viscosity, UV-curable organosilicon solution for Imprint imaging. We describe the technology fundamentals here. We demonstrate a durable, low surface energy template release coating, a UV-curable organosilicon etch barrier that cures with low dosage, and the equipment that allows for the high-precision orientation of the template/substrate system necessary for Imprint patterning. We have demonstrated printed features as small as 60 nm (not shown), compatibility with metal lift-off processing, functional optical devices including a micropolarizer array, and the ability to pattern high-aspect ratio, sub 0.25 micron features over a non-flat substrate.
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Nanoscale manufacturing enabled by Imprint Lithography
MRS Bulletin, 2008Co-Authors: Sidlgata V. SreenivasanAbstract:ABSTRACT Imprint Lithography has a remarkable patterning resolution of less than 5 nm, and it is simultaneously capable of patterning over large areas with long-range order. This combination enables a broad range of potential applications including terabit-density magnetic storage, CMOS integrated circuits, and nanowire molecular memory. This article provides a review of the status of Imprint Lithography for nanoscale manufacturing. First, representative nanoscale devices and their manufacturing requirements are reviewed, along with key patterning challenges that have to be overcome to enable these nanoscale applications. Two classes of top–down nanopatterning techniques, namely, photon-based Lithography and proximity mechanical nanopatterning (including Imprint Lithography), are described, followed by the three primary building blocks of Imprint Lithography: Imprint masks, tools, and materials. Theresults of the Lithography process are detailed in terms of process data such as long-range order in the placement and size of the nanostructures, process throughput, and overall cost considerations.
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N anoscale Manufacturing Enabled by Imprint Lithography
MRS Bulletin, 2008Co-Authors: Sidlgata V. SreenivasanAbstract:Imprint Lithography has a remarkable patterning resolution of less than 5 nm, and it is simultaneously capable of patterning over large areas with long-range order. This combination enables a broad range of potential applications including terabitdensity magnetic storage, CMOS integrated circuits, and nanowire molecular memory. This article provides a review of the status of Imprint Lithography for nanoscale manufacturing. First, representative nanoscale devices and their manufacturing requirements are reviewed, along with key patterning challenges that have to be overcome to enable these nanoscale applications. Two classes of top-down nanopatterning techniques, namely, photon-based Lithography and proximity mechanical nanopatterning (including Imprint Lithography), are described, followed by the three primary building blocks of Imprint Lithography: Imprint masks, tools, and materials. Theresults of the Lithography process are detailed in terms of process data such as long-range order in the placement and size of the nanostructures, process throughput, and overall cost considerations.
S. V. Sreenivasan - One of the best experts on this subject based on the ideXlab platform.
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Nanoshape Imprint Lithography for Fabrication of Nanowire Ultracapacitors
IEEE Transactions on Nanotechnology, 2016Co-Authors: Anshuman Cherala, Meghali Chopra, Akhila Mallavarapu, Shrawan Singhal, Ovadia Abed, Roger Bonnecaze, S. V. SreenivasanAbstract:Emerging nanoscale applications in energy, electronics, and medicine require high throughput patterning with complex shape control at the nanoscale that is beyond the capabilities of optical Lithography and block copolymer-based self-assembly. We introduce a technique for creating precise two-dimensional nanoshapes with sharp corners by Imprint Lithography, and apply it to enable shaped silicon nanowire capacitors that significantly exceed standard nanowire capacitor performance due to relative increase in surface area per unit projected area. The patterning technique employs atomic layer deposition to fabricate a template with diamond-like shapes consisting of corners with 2 nm radii of curvature. Template materials and chemical staining of the Imprint polymer enable precise imaging of the template and replicated resist. Continuum mechanics appears no longer applicable at the length scale of ~3 nm. A systematic increase in the radius of the Imprinted corner is observed contrary to predictions by a linear elastic continuum model shedding new light on shape relaxation of polymers, and on the limits of nanoshape replicability by Imprint Lithography. Novel diamond-shaped silicon nanowires (100-nm half-pitch) have been fabricated using nanoshape Imprint followed by metal-assisted chemical etching, and have been incorporated into shaped nanowire capacitors that exceed standard nanowire capacitors performance by ~90%. The 3-nm resolution limit does not degrade the performance of the shaped capacitor. This increased capacitance validates the ability to preserve nanoshape cross section during patterning and deep etching over large areas. Lithographic scaling to 10-nm half-pitch has the potential to further increase capacitance by a factor of 10.
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Mask replication using jet and flash Imprint Lithography
Photomask Technology 2011, 2011Co-Authors: K. Selinidis, D. J. Resnick, Dwayne L. Labrake, Chris Jones, Gary Doyle, Laura Brown, Joseph Michael Imhof, S. V. SreenivasanAbstract:The Jet and Flash Imprint Lithography (J-FILTM) process uses drop dispensing of UV curable resists to assist high resolution patterning for subsequent dry etch pattern transfer. The technology is actively being used to develop solutions for memory markets including Flash memory and patterned media for hard disk drives. It is anticipated that the lifetime of a single template (for patterned media) or mask (for semiconductor) will be on the order of 10 4 - 10 5 Imprints. This suggests that tens of thousands of templates/masks will be required to satisfy the needs of a manufacturing environment. Electron-beam patterning is too slow to feasibly deliver these volumes, but instead can provide a high quality "master" mask which can be replicated many times with an Imprint Lithography tool. This strategy has the capability to produce the required supply of "working" templates/masks. In this paper, we review the development of the mask form factor, Imprint replication tools and the semiconductor mask replication process. A Perfecta TM MR5000 mask replication tool has been developed specifically to pattern replica masks from an ebeam written master. Performance results, including image placement, critical dimension uniformity, and pattern transfer are covered in detail.
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High-density patterned media fabrication using jet and flash Imprint Lithography
Proceedings of SPIE, 2011Co-Authors: Zhengmao Ye, D. J. Resnick, Rick Ramos, Cynthia B. Brooks, Logan Simpson, John Fretwell, Scott Carden, Paul Hellebrekers, Dwayne L. Labrake, S. V. SreenivasanAbstract:ABSTRACT The Jet and Flash Imprint Lithography (J-FIL ® ) process uses drop dispensing of UV curable resists for high resolution patterning. Several applications, including patterned media, are better, and more economically served by a full substrate patterning process since the alignment requirements are minimal. Patterned media is particularly challenging because of the aggressive feature sizes necessary to achieve storage densities required for manufacturing beyond the current technology of perpendicular recording. In this paper, the key process steps for the application of J-FIL to pattern media fabrication are reviewed with special atte ntion to substrate cleaning, vapor adhesion of the adhesion layer and Imprint performance at >300 disk per hour. Also discussed are recent results for Imprinting discrete track patterns at half pitches of 24nm and bit patterned media patterns at densities of 1 Tb/in 2 . Keywords: Imprint Lithography, template, discrete track recording, bit pattern media, adhesion promoter, J-FIL, Jet and Flash Imprint Lithography
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Inspection of Imprint Lithography patterns for semiconductor and patterned media
Proceedings of SPIE, 2010Co-Authors: D. J. Resnick, K. Selinidis, John Fretwell, Gerard M. Schmid, Gaddi Haase, Lovejeet Singh, David Curran, Cindy Brooks, S. V. SreenivasanAbstract:Imprint Lithography has been shown to be an effective technique for replication of nano-scale features. Acceptance of Imprint Lithography for manufacturing will require demonstration that it can attain defect levels commensurate with the requirements of cost-effective device production. This work summarizes the results of defect inspections of semiconductor masks, wafers and hard disks patterned using Jet and Flash Imprint Lithography (J-FILTM). Inspections were performed with optical and e-beam based automated inspection tools. For the semiconductor market, a test mask was designed which included dense features (with half pitches ranging between 32 nm and 48 nm) containing an extensive array of programmed defects. For this work, both e-beam inspection and optical inspection were used to detect both random defects and the programmed defects. Analytical SEMs were then used to review the defects detected by the inspection. Defect trends over the course of many wafers were observed with another test mask using a KLA-T 2132 optical inspection tool. The primary source of defects over 2000 Imprints were particle related. For the hard drive market, it is important to understand the defectivity of both the template and the Imprinted disk. This work presents a methodology for automated pattern inspection and defect classification for Imprint-patterned media. Candela CS20 and 6120 tools from KLA-Tencor map the optical properties of the disk surface, producing highresolution grayscale images of surface reflectivity, scattered light, phase shift, etc. Defects that have been identified in this manner are further characterized according to the morphology
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Patterned wafer defect density analysis of step and flash Imprint Lithography
Journal of Vacuum Science & Technology B, 2008Co-Authors: I. Mcmackin, K. Selinidis, J. Maltabes, W Martin, J Perez, Frank Y. Xu, D. J. Resnick, S. V. SreenivasanAbstract:Acceptance of Imprint Lithography for complementary metal-oxide semiconductor (CMOS) manufacturing will require demonstration that it can attain defect levels commensurate with the requirements of cost-effective device production. This article specifically focuses on this challenge presenting the current status of defect reduction in step and flash Imprint Lithography (S-FIL). The results of defect inspections of wafers patterned using S-FIL are summarized. The masks or templates used to Imprint wafers for this study were designed specifically to facilitate automated defect inspection. The templates were made by employing CMOS industry standard materials and exposure tools. The primary wafer inspection was performed using a KLA Tencor-2132 (KT-2132) automated patterned wafer inspection tool. Additional Imprint inspections were carried out on a KT-eS32 e-beam inspection system. The first section of the article provides a brief background of S-FIL technology. Next, the defect types and potential sources are...
D. J. Resnick - One of the best experts on this subject based on the ideXlab platform.
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Mask replication using jet and flash Imprint Lithography
Photomask Technology 2011, 2011Co-Authors: K. Selinidis, D. J. Resnick, Dwayne L. Labrake, Chris Jones, Gary Doyle, Laura Brown, Joseph Michael Imhof, S. V. SreenivasanAbstract:The Jet and Flash Imprint Lithography (J-FILTM) process uses drop dispensing of UV curable resists to assist high resolution patterning for subsequent dry etch pattern transfer. The technology is actively being used to develop solutions for memory markets including Flash memory and patterned media for hard disk drives. It is anticipated that the lifetime of a single template (for patterned media) or mask (for semiconductor) will be on the order of 10 4 - 10 5 Imprints. This suggests that tens of thousands of templates/masks will be required to satisfy the needs of a manufacturing environment. Electron-beam patterning is too slow to feasibly deliver these volumes, but instead can provide a high quality "master" mask which can be replicated many times with an Imprint Lithography tool. This strategy has the capability to produce the required supply of "working" templates/masks. In this paper, we review the development of the mask form factor, Imprint replication tools and the semiconductor mask replication process. A Perfecta TM MR5000 mask replication tool has been developed specifically to pattern replica masks from an ebeam written master. Performance results, including image placement, critical dimension uniformity, and pattern transfer are covered in detail.
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High-density patterned media fabrication using jet and flash Imprint Lithography
Proceedings of SPIE, 2011Co-Authors: Zhengmao Ye, D. J. Resnick, Rick Ramos, Cynthia B. Brooks, Logan Simpson, John Fretwell, Scott Carden, Paul Hellebrekers, Dwayne L. Labrake, S. V. SreenivasanAbstract:ABSTRACT The Jet and Flash Imprint Lithography (J-FIL ® ) process uses drop dispensing of UV curable resists for high resolution patterning. Several applications, including patterned media, are better, and more economically served by a full substrate patterning process since the alignment requirements are minimal. Patterned media is particularly challenging because of the aggressive feature sizes necessary to achieve storage densities required for manufacturing beyond the current technology of perpendicular recording. In this paper, the key process steps for the application of J-FIL to pattern media fabrication are reviewed with special atte ntion to substrate cleaning, vapor adhesion of the adhesion layer and Imprint performance at >300 disk per hour. Also discussed are recent results for Imprinting discrete track patterns at half pitches of 24nm and bit patterned media patterns at densities of 1 Tb/in 2 . Keywords: Imprint Lithography, template, discrete track recording, bit pattern media, adhesion promoter, J-FIL, Jet and Flash Imprint Lithography
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Inspection of Imprint Lithography patterns for semiconductor and patterned media
Proceedings of SPIE, 2010Co-Authors: D. J. Resnick, K. Selinidis, John Fretwell, Gerard M. Schmid, Gaddi Haase, Lovejeet Singh, David Curran, Cindy Brooks, S. V. SreenivasanAbstract:Imprint Lithography has been shown to be an effective technique for replication of nano-scale features. Acceptance of Imprint Lithography for manufacturing will require demonstration that it can attain defect levels commensurate with the requirements of cost-effective device production. This work summarizes the results of defect inspections of semiconductor masks, wafers and hard disks patterned using Jet and Flash Imprint Lithography (J-FILTM). Inspections were performed with optical and e-beam based automated inspection tools. For the semiconductor market, a test mask was designed which included dense features (with half pitches ranging between 32 nm and 48 nm) containing an extensive array of programmed defects. For this work, both e-beam inspection and optical inspection were used to detect both random defects and the programmed defects. Analytical SEMs were then used to review the defects detected by the inspection. Defect trends over the course of many wafers were observed with another test mask using a KLA-T 2132 optical inspection tool. The primary source of defects over 2000 Imprints were particle related. For the hard drive market, it is important to understand the defectivity of both the template and the Imprinted disk. This work presents a methodology for automated pattern inspection and defect classification for Imprint-patterned media. Candela CS20 and 6120 tools from KLA-Tencor map the optical properties of the disk surface, producing highresolution grayscale images of surface reflectivity, scattered light, phase shift, etc. Defects that have been identified in this manner are further characterized according to the morphology
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Linewidth roughness characterization in step and flash Imprint Lithography
Photomask and Next-Generation Lithography Mask Technology XV, 2008Co-Authors: Gerard M. Schmid, Cynthia B. Brooks, Dwayne L. Labrake, E. Thompson, Niyaz Khusnatdinov, D. J. ResnickAbstract:Despite the remarkable progress made in extending optical Lithography to deep sub-wavelength imaging, the limit for the technology seems imminent. At 22nm half pitch design rules, neither very high NA tools (NA 1.6), nor techniques such as double patterning are likely to be sufficient. One of the key challenges in patterning features with these dimensions is the ability to minimize feature roughness while maintaining reasonable process throughput. This limitation is particularly challenging for electron and photon based NGL technologies, where fast chemically amplified resists are used to define the patterned images. Control of linewidth roughness (LWR) is critical, since it adversely affects device speed and timing in CMOS circuits. Imprint Lithography has been included on the ITRS Lithography Roadmap at the 32 and 22 nm nodes. This technology has been shown to be an effective method for replication of nanometer-scale structures from a template (Imprint mask). As a high fidelity replication process, the resolution of Imprint Lithography is determined by the ability to create a master template having the required dimensions. Although the Imprint process itself adds no additional linewidth roughness to the patterning process, the burden of minimizing LWR falls to the template fabrication process. Non chemically amplified resists, such as ZEP520A, are not nearly as sensitive but have excellent resolution and can produce features with very low LWR. The purpose of this paper is to characterize LWR for the entire Imprint Lithography process, from template fabrication to the final patterned substrate. Three experiments were performed documenting LWR in the template, Imprint, and after pattern transfer. On average, LWR was extremely low (less than 3nm, 3σ), and independent of the processing step and feature size.
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Controlling Linewidth Roughness in Step and Flash Imprint Lithography
24th European Mask and Lithography Conference, 2008Co-Authors: Gerard M. Schmid, D. J. Resnick, Cynthia B. Brooks, E. Thompson, Niyaz Khusnatdinov, Dwayne Labrake, Jordan Owens, Arnie Ford, Shiho Sasaki, Nobuhito ToyamaAbstract:Despite the remarkable progress made in extending optical Lithography to deep sub-wavelength imaging, the limit for the technology seems imminent. At 22nm half pitch design rules, neither very high NA tools (NA 1.6), nor techniques such as double patterning are likely to be sufficient. One of the key challenges in patterning features with these dimensions is the ability to minimize feature roughness while maintaining reasonable process throughput. This limitation is particularly challenging for electron and photon based NGL technologies, where fast chemically amplified resists are used to define the patterned images. Control of linewidth roughness (LWR) is critical, since it adversely affects device speed and timing in CMOS circuits. Imprint Lithography has been included on the ITRS Lithography Roadmap at the 32 and 22 nm nodes. This technology has been shown to be an effective method for replication of nanometer-scale structures from a template (Imprint mask). As a high fidelity replication process, the resolution of Imprint Lithography is determined by the ability to create a master template having the required dimensions. Although the Imprint process itself adds no additional linewidth roughness to the patterning process, the burden of minimizing LWR falls to the template fabrication process. Non chemically amplified resists, such as ZEP520A, are not nearly as sensitive but have excellent resolution and can produce features with very low LWR. The purpose of this paper is to characterize LWR for the entire Imprint Lithography process, from template fabrication to the final patterned substrate. Three experiments were performed documenting LWR in the template, Imprint, and after pattern transfer. On average, LWR was extremely low (less than 3nm, 3sigma), and independent of the processing step and feature size.
Carsten Werner - One of the best experts on this subject based on the ideXlab platform.
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biologically inspired omniphobic surfaces by reverse Imprint Lithography
Advanced Materials, 2014Co-Authors: Rene Hensel, Andreas Finn, Ralf Helbig, Hansgeorg Braun, Christoph Neinhuis, Wolfjoachim Fischer, Carsten WernerAbstract:: Springtail skin morphology is translated into robust omniphobic polymer membranes by reverse Imprint Lithography. The combination of overhanging cross-sections and their arrangement in a self-supporting comblike pattern are crucial for mechanically stable coatings that can be even applied to curved surfaces.
Bingheng Lu - One of the best experts on this subject based on the ideXlab platform.
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Room-temperature capillary-Imprint Lithography for making micro-/nanostructures in large areas
Journal of Vacuum Science & Technology. B. Nanotechnology and Microelectronics: Materials Processing Measurement and Phenomena, 2010Co-Authors: Xiangdong Ye, Yucheng Ding, Yugang Duan, Bingheng LuAbstract:Compared to Imprint techniques under the driving condition of external Imprint pressure, Imprint Lithography under capillary force has the advantages of being suitable to produce large feature patterns, simple mold structure, very low Imprint pressure, and conformal contact between the mold and the substrate. However, in existing capillary-force Lithography, the necessary heating process will bring problems, such as separation between the mold and the substrate, long Imprint time, shorter lifetime of the mold, etc. In this article, the authors propose a technique of room-temperature capillary-Imprint Lithography which is applied to making both micro- and nanostructures simultaneously in large areas under low temperature. In order to prevent the polydimethylsiloxane mold from swelling in the Imprint process, a new ultraviolet curable resist is introduced in the Imprint process. This resist contains no solvents and has a wide range of viscosity. Through the experiment, three-dimensional microstructures are ...
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Development of a step micro-Imprint Lithography tool
Journal of Micromechanics and Microengineering, 2007Co-Authors: Yucheng Ding, Bingheng LuAbstract:This paper proposes a UV Imprint Lithography process which uses a soft PDMS mold to transfer high resolution patterns at room temperature and low pressures conditions, and emphasizes reporting the development of the step micro-Imprint Lithography (SIL) tool for sub-micrometer patterning. The overall design of the machine and implementation of key units are described in detail. To eliminate the distortion of the soft mold in the loading process, distortion reduction by a load release process was proposed and applied in the SIL machine. By optimizing the loading process curve, an Imprinting process curve was established. Furthermore, an overlay process using the load release and alignment error pre-compensation method was proposed to achieve high precision overlay for the SIL tool. Finally, various experiments were conducted to test the performance of the SIL apparatus. The experimental results show that the step micro-Imprint Lithography tool together with the proposed processes can replicate the sub-micrometer patterns with different feature sizes, different structures and different pattern sizes.
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Study of Carbon Nano-Tube Photo-electronic Devices by Nano-Imprint Lithography
2007 International Nano-Optoelectronics Workshop, 2007Co-Authors: Yucheng Ding, Bingheng LuAbstract:Nano-Imprint Lithography (NIL) technology is presented to fabricate carbon nano-tube (CNT) arrays for field emission (FE) and sensor devices by process control and optimization. Results reveal that the CNT arrays are high resolution and fidelity.
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A nano-scale alignment method for Imprint Lithography
Frontiers of Mechanical Engineering in China, 2006Co-Authors: Li Wang, Bingheng Lu, Yucheng DingAbstract:A novel nano-scale alignment technique based on moire signal for room-temperature Imprint Lithography in the submicron realm is proposed. The moire signals generated by two pairs of quadruple gratings on mold and wafer are optically projected onto two photo-detector arrays, then the detected moire signals are used to estimate the alignment errors in the x and y directions. The experiment results indicate that complex differential moire signal is sensitive to relative displacement of the mold and wafer, and the alignment accuracy obtained in the x and y directions and in ϑ are ±20 nm, ±25 nm and ±1 μrad (3σ), respectively. They can meet the requirements of alignment accuracy for submicron Imprint Lithography.
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Distortion reduction by load release for Imprint Lithography
Microelectronic Engineering, 2006Co-Authors: Hansong Li, Yucheng Ding, Yiping Tang, Bingheng LuAbstract:Due to the light source limitation and prohibitive cost inherent in conventional photoLithography, various nontraditional patterning technologies, such as Imprint Lithography, electron beam or X-ray Lithography have been attempted over the past 10 years. In this paper, a UV Imprint Lithography process is introduced for patterning sub-micrometer structures by using a soft PDMS mould, and an Imprint experimental device with a loading mechanism driven by PZT for generating a time-variant load is described. As shown experimentally, an increased pressing load will reduce the thickness of the resist layer, leading to a reliable etching-through of the resist. It is found, however, that the mechanical pressing can generate geometrical distortion on the patterned resist mainly due to the elasticity. Incorporated with the use of a low viscosity photo-curable resist, a loading process with a load release step is proposed to reduce the geometrical distortion on the resist patterns. In the loading process, the loading force is partially released after the press peak but before the resist curing. Such a loading process can reduce the elastic distortion while attaining a thin remained resist layer. It is shown that this loading process, called Distortion Reduction by Load Release or DRLR simply can be combined with an Imprint process for different patterning areas and feature sizes.
