The Experts below are selected from a list of 5472 Experts worldwide ranked by ideXlab platform
James D. Meindl - One of the best experts on this subject based on the ideXlab platform.
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a stochastic wire length distribution for gigascale integration gsi ii applications to clock frequency power dissipation and chip size estimation
IEEE Transactions on Electron Devices, 1998Co-Authors: Jeffrey A. Davis, Vivek De, James D. MeindlAbstract:For pt.I see ibid., vol.45, no.3, pp.580-9 (Mar. 1998). Based on Rent's Rule, a well-established empirical relationship, a complete wire-length distribution for on-chip random logic networks is used to enhance a critical path model; to derive a preliminary dynamic power dissipation model; and to describe optimal architectures for multilevel wiring networks that provide maximum Interconnect Density and minimum chip size.
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A stochastic wire length distribution for gigascale integration (GSI)
Proceedings of CICC 97 - Custom Integrated Circuits Conference, 2024Co-Authors: Jeffrey A. Davis, James D. MeindlAbstract:Based on Rent's Rule, a well established empirical relationship, a rigorous derivation of a complete wire length distribution for on-chip random logic networks is performed. This distribution is used to enhance a critical path model; to derive a preliminary dynamic power dissipation model; and to describe optimal architectures for multilevel wiring networks that provide maximum Interconnect Density.
Jeffrey A. Davis - One of the best experts on this subject based on the ideXlab platform.
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a stochastic wire length distribution for gigascale integration gsi ii applications to clock frequency power dissipation and chip size estimation
IEEE Transactions on Electron Devices, 1998Co-Authors: Jeffrey A. Davis, Vivek De, James D. MeindlAbstract:For pt.I see ibid., vol.45, no.3, pp.580-9 (Mar. 1998). Based on Rent's Rule, a well-established empirical relationship, a complete wire-length distribution for on-chip random logic networks is used to enhance a critical path model; to derive a preliminary dynamic power dissipation model; and to describe optimal architectures for multilevel wiring networks that provide maximum Interconnect Density and minimum chip size.
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A stochastic wire length distribution for gigascale integration (GSI)
Proceedings of CICC 97 - Custom Integrated Circuits Conference, 2024Co-Authors: Jeffrey A. Davis, James D. MeindlAbstract:Based on Rent's Rule, a well established empirical relationship, a rigorous derivation of a complete wire length distribution for on-chip random logic networks is performed. This distribution is used to enhance a critical path model; to derive a preliminary dynamic power dissipation model; and to describe optimal architectures for multilevel wiring networks that provide maximum Interconnect Density.
Rao Tummala - One of the best experts on this subject based on the ideXlab platform.
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reliability of fine pitch μ m diameter microvias for high Density Interconnects
IEEE Transactions on Components Packaging and Manufacturing Technology, 2020Co-Authors: Shreya Dwarakanath, Madhavan Swaminathan, Takenori Kakutani, Daichi Okamoto, P M Raj, Rao TummalaAbstract:Downscaling of package wiring has been the singular focus to achieve higher logic-memory Interconnect Density to meet next-generation needs for high-bandwidth computing. This article presents, for the first time, a systematic modeling and experimental study of sub-5- $\mu \text{m}$ -diameter microvia reliability. Geometry design considerations and build-up dielectric material properties in evaluating the microvia fatigue life are investigated. Finally, experimental thermal-cycling reliability results of sub-5- $\mu \text{m}$ -diameter microvias are correlated with the modeling results.
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next generation of 2 7 micron ultra small microvias for 2 5d panel redistribution layer by using laser and photolithography technologies
Electronic Components and Technology Conference, 2019Co-Authors: Fuhan Liu, Chandrasekharan Nair, Bartlet Deprospo, Gaurav Khurana, Atom Watanabe, Atsushi Kubo, Cheng Ping Lin, Toshiyuki Makita, Naoki Watanabe, Rao TummalaAbstract:Microvia is the vertical Interconnect structure for multi-layer redistribution layers (RDLs) in high-Density Interconnect (HDI) printed circuit boards (PCBs), HDI package substrates, 2.5D interposers and fan-out packages. Three technologies such as photolithography, UV laser and excimer laser have been used to form small microvias (≤ 20 µm diameter) in polymer dielectrics. All the three above mentioned technologies are studied and compared in the work presented in this paper. Photovia was first introduced by IBM for Surface Laminar Circuit technology and it has scaled down from 125 µm then to below 10 µm today. The smallest photovia demonstrated is 2 µm in diameter by using 365 nm photolithography in 5 µm thick TOK photo-imageable dielectric (PID) (IF4605) film. Photovias of 3 µm diameter were also demonstrated in 5 µm thick Taiyo Ink dielectric dry film material (PDM) which passed 1,500 thermal cycles (-55 C to 125 C). The limitation of photovia technology is the availability and cost of photo-sensitive dielectric materials with the required electrical, mechanical, thermal and chemical properties. The state-of-the-art microvia diameter is 20 µm by using conventional high-speed UV laser technologies. Multi-layer RDL with microvias and trenches of 4 µm feature sizes are simultaneously fabricated in a 7 µm thick Ajinomoto Build-up Film (ABF) with small fillers by using excimer laser and passed 1,000 thermal cycles (-55 C to 125 C). This paper demonstrates a novel picosecond UV laser technology to push the limits of low-cost UV laser technology by optimizing laser parameters and dielectric materials. The Cornerstone picosecond UV laser tool from ESI is capable of producing output power of 16W at 355 nm wavelength. The pulse duration is 5 ps which minimizes the heat-affected zone of polymer dielectric and the high (80 MHz) repetition rate enables this laser to be used in high throughput manufacturing processes. Microvias with minimum diameter of < 7 µm were fabricated in 5 µm thick ABF with small fillers and in 7 µm thick novel Panasonic low stress dielectric film-S (PLS-S), by using 355 nm picosecond UV laser tool. These ABF and PLS-S films are non-photosensitive dielectric materials. This is the first demonstration of very small microvias (< 7 µm) in polymer dielectrics using UV laser ablation. The motivation of this work is to address the high RDL Interconnect Density requirements for 2.5D interposer and high Density (HD) fan-out packages. The next generation of low-cost, ultra-small microvias will (1) Increase the RDL I/O Density, (2) Meet fine bump pitch requirements, (3) Reduce the metal layer count for package substrate RDL, (4) Fill the gap between semiconductor back-end-of-line (BEOL) process and semi-additive process (SAP) and thereby (5) Improve the packaging performance at lower costs.
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via in trench a revolutionary panel based package rdl configuration capable of 200 450 io mm layer an innovation for more than moore system integration
Electronic Components and Technology Conference, 2017Co-Authors: Fuhan Liu, Chandrasekharan Nair, Venky Sundaram, Rui Zhang, Atsushi Kubo, Tomoyuki Ando, Hang Chen, Kwon Sang Lee, Rao TummalaAbstract:This paper presents, for the first time, a novel silicon damascene like via-in-trench (ViT) Interconnect for panel-scale package redistribution layer (RDL) configuration. The panel scale damascene RDL in this paper comprises of ultra-fine copper embedded trenches and microvias with diameter equal to the width of trenches using a 5 µm thick dry film photosensitive dielectric. A 140 µm thick glass substrate is used as the core material. The new panel scalable ViT Interconnect is targeted for low cost, next generation 2D and 2.5D interposers and high Density packages. The ViT RDL is integrated with 2 µm diameter microvias with 2.5 µm half-line pitch copper traces embedded in a 5 µm thick dry film photo-imageable dielectric (PID) polymer. This RDL integration directly translates to IO Density of 200 IO/mm/layer. IO/mm/layer, as defined by Intel, is the number of wires routed per mm of die edge on each layer of package substrate. There is no capture pad required for ViT Interconnect demonstrated in this paper. The routing Cu trace is aligned directly on top of microvia instead of the conventional via-capture pad-trace Interconnect configuration. The fabrication of such a high Density RDL is achieved by patterning a trench over via and then fully filling with copper. Conventional i-line (365 nm) photolithography, widely used for patterning PWB and package substrates, was employed for fine trenches formation as well as small microvias in the PID. An advanced 5 µm thick PID film IF4605 was selected for build-up layers. Experimental results showed that microvias with diameters of 2 µm and trenches with half-line pitch of 2.5 µm were achieved in 5 µm thick IF dry film. Traces with half-line pitch of 1 µm were demonstrated in a 3 µm thick liquid photo resist film. The aspect ratios were 2.5 for dry film PID and 3 for liquid photo-resist respectively. The best Interconnection Density in terms of IO/mm/layer was calculated to be 200 using dry film PID and can be extended to 450 using thinner PIDs. For comparison, the IO Density for state-of-the-art organic interposer was 40 by using semi-additive process (SAP). The embedded trench technology breaks through the limit of SAP and achieves 5-10X Interconnect Density compared to SAP. The ViT Interconnect is a revolutionary package RDL configuration to meet the requirements of future package substrates for high performance computing, high bandwidth memory and micro-miniaturized system applications. The demonstration of ViT RDL configuration on thin glass substrate with L/S/Via/Pitch of 2.5/2.5/2/20 µm using embedded trench approach will be presented and the fabrication processes will be described in detail.
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design and demonstration of a 2 5 d glass interposer bga package for high bandwidth and low cost
IEEE Transactions on Components Packaging and Manufacturing Technology, 2017Co-Authors: Brett Sawyer, Chandrasekharan Nair, Venky Sundaram, Vanessa Smet, Yuya Suzuki, Ryuta Furuya, Tingchia Huang, Kadappan Panayappan, Rao TummalaAbstract:Consumer demand for mobile services is expected to grow with the continued proliferation of connected devices including smartphones, wearables, and Internet of things. As a result, high-performance computing systems that support the core network and cloud infrastructures for these connected devices require unprecedented die-to-die bandwidth at low latency. To achieve next-generation performance requirements and to apply to commercial products, fundamental parameters for 2.5-D interposers are considered including: 1) high Interconnect Density at short Interconnect length; 2) low power consumption; and 3) low packaging cost. The 2.5-D glass interposer described in this paper is superior to silicon interposer in cost and electrical performance, and to organic interposer in Interconnect Density. This paper describes a 2.5-D glass interposer as a ball grid array (BGA) package to achieve high bandwidth at low cost to improve bandwidth per unit watt signal power per unit dollar cost (BWF) compared to both silicon and organic interposers. Due to its high modulus and excellent surface finish, glass affords ultrafine line lithography to form high-Density Interconnects comparable to silicon, and the process described in this paper goes beyond silicon back-end-of-line processes by implementing a double-side semi-additive process (SAP) at increased copper layer thickness. This thicker metallization results in reduced conductor losses and improved bandwidth per channel compared to silicon. In addition, the low loss tangent of glass reduces dielectric losses in nets requiring through vias including clock distribution and high-speed off-package signals. Availability of glass in thin panel as well as in roll-to-roll formats beyond 500 mm in size reduces packaging cost compared to 300-mm wafer silicon interposer. The focus of this paper is on the integration of three enabling technologies: 1) advanced SAP for high-Density redistribution layers (RDLs); 2) excimer laser ablation of RDL vias; and 3) fine-pitch thermocompression bonding with copper pillar die assembly—for a 2.5-D glass interposer at Interconnect densities comparable to that of silicon to achieve terabit per second interdie bandwidth at highest BWF.
Eric Beyne - One of the best experts on this subject based on the ideXlab platform.
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novel temporary bonding and debonding solutions enabling an ultrahigh interonnect Density fo wlp structure assembly with quasi zero die shift
2019 International Wafer Level Packaging Conference (IWLPC), 2019Co-Authors: Arnita Podpod, Alain Phommahaxay, Andy Miller, Gerald Beyer, Eric Beyne, Alice Guerrero, Xiao Liu, Kim Yess, Kim Arnold, Pieter BexAbstract:Next-generation temporary bonding adhesive material is introduced into imec's high Interconnect Density flip chip on fan-out wafer-level package (FC FOWLP) concept [1], [2]. After molding on silicon substrates, an ultralow die shift with an average of $ die-to-carrier mismatch and warpage of $ were achieved in a full 300-mm wafer. These values are orders of magnitude improvement over results reported in literature and has major implications on the processing of overmolded substrates. The combination of this low warp and ultralow distortion opens the possibility for fine-pitch RDL combined with a chip-first approach, which was impossible until now. The evolution of warpage and die shift through multiple processing steps will also be discussed in this paper.
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high Density and high bandwidth chip to chip connections with 20μm pitch flip chip on fan out wafer level package
2018 International Wafer Level Packaging Conference (IWLPC), 2018Co-Authors: Velenis D Podpod, Alain Phommahaxay, Pieter Bex, Ferenc Fodor, Ej Marinissen, Kenneth June Rebibis, Andy Miller, Gerald Beyer, Eric BeyneAbstract:Various Fan-Out Wafer Level Packaging (FO-WLP) approaches have been developed and established over the past years to answer the increasing need for high data rates, wide I/O count and the demand for increase function integration on package. Imec has been working on a novel 300mm FO-WLP concept that enables 20$\mu$m pitch Interconnect Density: Flip-Chip on FO-WLP. Major challenges and solutions are reported in this paper. Results demonstrate die placement alignment of < 3$\mu$m, which is suitable to allow stacking for high Density Interconnect. Connections between the assembled dies were intact before and after molding.
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ultra fine pitch 3d integration using face to face hybrid wafer bonding combined with a via middle through silicon via process
Electronic Components and Technology Conference, 2016Co-Authors: Soonwook Kim, Andy Miller, Gerald Beyer, Mikael Detalle, Lan Peng, P Nolmans, N Heylen, Dimitrios Velenis, Eric BeyneAbstract:High performance 3D integration Systems need a higher Interconnect Density between the die than traditional µbump Interconnects can offer. For ultra-fine pitches Interconnect pitches below 5µm a different solution is required. This paper describes a hybrid wafer-to-wafer (W2W) bonding approach that uses Cu damascene patterned surface bonding, allowing to scale down the Interconnection pitch below 5 µm, potentially even down to 1µm, depending on the achievable W2W bonding accuracy. The bonding method is referred to as hybrid bonding since the bonding of the Cu/dielectric damascene surfaces leads simultaneously to metallic and dielectric bonding. In this paper, the integration flow for 300mm hybrid wafer bonding at 3.6µm and 1.8µm pitch will be described using a novel, alternative, non-oxide Cu/dielectric damascene process. Optimization of the surface preparation before bonding will be discussed. Of particular importance is the wafer chemical-mechanical-polishing (CMP) process and the pre-bonding wafer treatment. Using proper surface activation and very low roughness dielectrics, void-free room temperature bonding can be achieved. High bonding strengths are obtained, even using low temperature anneal (250°C). The process flow also integrates the use of a 5µm diameter, 50µm deep via-middle through-silicon-vias (TSV) to connect the wafer interfaces to the external wafer backside.
Michael P Beakes - One of the best experts on this subject based on the ideXlab platform.
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an 8x 10 gb s source synchronous i o system based on high Density silicon carrier Interconnects
IEEE Journal of Solid-state Circuits, 2012Co-Authors: Timothy O Dickson, Yong Liu, Sergey V Rylov, Bing Dang, Cornelia K Tsang, Paul S Andry, John F Bulzacchelli, Herschel A Ainspan, Lavanya Turlapati, Michael P BeakesAbstract:A source synchronous I/O system based on high-Density silicon carrier Interconnects is introduced. Benefiting from the advantages of advanced silicon packaging technologies, the system uses 50 μm-pitch μC4s to reduce I/O cell size and fine-pitch Interconnects on silicon carrier to achieve record-breaking Interconnect Density. An I/O architecture is introduced with link redundancy such that any link can be taken out of service for periodic recalibration without interrupting data transmission. A timing recovery system using two phase rotators shared across all bits in a receive bus is presented. To demonstrate these concepts, an I/O chipset using this architecture is fabricated in 45 nm SOI CMOS technology. It includes compact DFE-IIR equalization in the receiver, as well as a new all-CMOS phase rotator. The chipset is mounted to a silicon carrier tile via Pb-free SnAg μ C4 solder bumps. Chip-to-chip communication is achieved over ultra-dense Interconnects with pitches of between 8 μm and 22 μm. 8 × 10-Gb/s data is received over distances up to 4 cm with a link energy efficiency of 5.3 pJ/bit from 1 V TX and RX power supplies. 8 × 9-Gb/s data is recovered from a 6-cm link with 16.3 dB loss at 4.5 GHz with an efficiency of 6.1 pJ/bit.
