The Experts below are selected from a list of 168 Experts worldwide ranked by ideXlab platform
Kang L Wang - One of the best experts on this subject based on the ideXlab platform.
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NANOARCH - Spin wave nanofabric update
Proceedings of the 2012 IEEE ACM International Symposium on Nanoscale Architectures - NANOARCH '12, 2012Co-Authors: Juan G. Alzate, Kang L Wang, Pramey Upadhyaya, Mark Lewis, J. Nath, Yen-ting Lin, Kin L. Wong, S. S. Cherepov, P. Khalili Amiri, Joshua L. HockelAbstract:We provide a progress update on the spin wave nanofabric. The nanofabric comprises magneto-electric cells and spin wave buses serving for spin wave propagation. The magneto-electric cells are used as the input/output ports for information transfer between the charge and the spin domains, while information processing inside the nanofabric is via spin waves only. Information is encoded into the phase of the propagating spin wave, which makes it possible to utilize waveguides as passive Logic elements and take the advantage of using wave superposition for data processing. This provides a fundamental advantage over the conventional transistor-based Logic Circuitry allowing for functional throughput enhancement and power consumption minimization at the same time. We present recent accomplishments in the magneto-electric element development and integration with spin wave buses. In particular, we show the excitation and detection of the spin waves via multiferroic elements. In addition, we present different approaches to magnonic Logic circuit engineering and provide the comparison with CMOS by mapping the designs to 45nm NANGATE standard cell libraries. The estimates show more than 40X power reduction and 53X area reduction for magnonic circuits. These results illustrate the potential advantages over conventional charge based electronics that could be a route to beyond CMOS Logic Circuitry.
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spin wave magnetic nanofabric a new approach to spin based Logic Circuitry
IEEE Transactions on Magnetics, 2008Co-Authors: Alexander Khitun, Kang L WangAbstract:We describe a magnetic nanofabric, which may provide a route to building reconfigurable spin-based Logic circuits compatible with conventional electron-based devices. A distinctive feature of magnetic nanofabric is that a bit of information is encoded into the phase of the spin wave signal. This makes it possible to transmit information without the use of electric current and to utilize wave interference for useful Logic functionality. The basic elements include voltage-to-spin-wave and wave-to-voltage converters, spin waveguides, a spin wave modulator, and a magnetoelectric cell. We illustrate the performance of the basic elements by experimental data and the results of numerical modeling. The combination of the basic elements leads us to construct magnetic circuits for NOT and majority Logic gates. Logic gates such as AND, OR, NAND, and NOR are shown as the combination of NOT and reconfigurable majority gates. Examples of computational architectures such as a multibit processor and a cellular nonlinear network are described. The main advantage of the proposed magnetic nanofabric is its ability to realize Logic gates with fewer devices than in CMOS-based circuits. Potentially, the area of the elementary reconfigurable majority gate can be scaled down to 0.1 mum2. We also discuss the disadvantages and limitations of the magnetic nanofabric.
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spin wave magnetic nanofabric a new approach to spin based Logic Circuitry
arXiv: Other Condensed Matter, 2007Co-Authors: Alexander Khitun, Mingqiang Bao, Kang L WangAbstract:We propose and describe a magnetic NanoFabric which provides a route to building reconfigurable spin-based Logic circuits compatible with conventional electron-based devices. A distinctive feature of the proposed NanoFabric is that a bit of information is encoded into the phase of the spin wave signal. It makes possible to transmit information without the use of electric current and utilize wave interference for useful Logic functionality. The basic elements include voltage-to-spin wave and wave-to-voltage converters, spin waveguides, a modulator, and a magnetoelectric cell. As an example of a magnetoelectric cell, we consider a two-phase piezoelectric-piezomagnetic system, where the spin wave signal modulation is due to the stress-induced anisotropy caused by the applied electric field. The performance of the basic elements is illustrated by experimental data and results of numerical modeling. The combination of the basic elements let us construct magnetic circuits for NOT and Majority Logic gates. Logic gates AND, OR, NAND and NOR are shown to be constructed as the combination of NOT and a reconfigurable Majority gates. The examples of computational architectures such as Cellular Automata, Cellular Nonlinear Network and Field Programmable Gate Array are described. The main advantage of the proposed NanoFabric is in the ability to realize Logic gates with less number of devices than it required for CMOS-based circuits. Potentially, the area of the elementary reconfigurable Majority gate can be scaled down to 0.1um2. The disadvantages and limitations of the proposed NanoFabric are discussed.
Alexander Khitun - One of the best experts on this subject based on the ideXlab platform.
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Magnonic holographic co-processor: An approach to energy-efficient complementary Logic Circuitry
2015 Fourth Berkeley Symposium on Energy Efficient Electronic Systems (E3S), 2015Co-Authors: Alexander KhitunAbstract:Power consumption has emerged as the major problem limiting the scalability and the functional throughput of modern Logic devices [1]. This problem has stimulated a great deal of interest to research alternative technologies, which may overcome the constraints inherent to complementary metal-oxide-semiconductor (CMOS)-based Circuitry and provide a route to more functional and less power-consuming Logic devices. Spintronics is one of the possible directions [2]. The utilization of spin opened a new horizon for the development of non-volatile memory and Logic elements. It also offers novel approaches to data transfer. The integration of the spin-based components will require new architecture solutions. In this work, we discuss the possibility of building Magnonic Holographic Co-Processor (MHcP) aimed to complement CMOS in special task data processing. The main advantage of MHcP is combination of memory and Logic in one unit. This idea is illustrated in Figure 1. On the left side, it is shown the Von Neumann architecture scheme. It consists of Memory, Control Unit and Arithmetic Logic Unit. The separation between the memory and the Logic units is an attribute of the traditional architecture. On the right side of Figure 1, there are shown the schematics of MHcP, where the large portion of memory is embedded into the magnonic holographic Logic unit. This architecture solution allows significantly minimize power consumption required for memory addressing and information transfer between the units. The advantage is most prominent in special task data processing requiring large amount of memory resources (e.g. database search).
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spin wave magnetic nanofabric a new approach to spin based Logic Circuitry
IEEE Transactions on Magnetics, 2008Co-Authors: Alexander Khitun, Kang L WangAbstract:We describe a magnetic nanofabric, which may provide a route to building reconfigurable spin-based Logic circuits compatible with conventional electron-based devices. A distinctive feature of magnetic nanofabric is that a bit of information is encoded into the phase of the spin wave signal. This makes it possible to transmit information without the use of electric current and to utilize wave interference for useful Logic functionality. The basic elements include voltage-to-spin-wave and wave-to-voltage converters, spin waveguides, a spin wave modulator, and a magnetoelectric cell. We illustrate the performance of the basic elements by experimental data and the results of numerical modeling. The combination of the basic elements leads us to construct magnetic circuits for NOT and majority Logic gates. Logic gates such as AND, OR, NAND, and NOR are shown as the combination of NOT and reconfigurable majority gates. Examples of computational architectures such as a multibit processor and a cellular nonlinear network are described. The main advantage of the proposed magnetic nanofabric is its ability to realize Logic gates with fewer devices than in CMOS-based circuits. Potentially, the area of the elementary reconfigurable majority gate can be scaled down to 0.1 mum2. We also discuss the disadvantages and limitations of the magnetic nanofabric.
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spin wave magnetic nanofabric a new approach to spin based Logic Circuitry
arXiv: Other Condensed Matter, 2007Co-Authors: Alexander Khitun, Mingqiang Bao, Kang L WangAbstract:We propose and describe a magnetic NanoFabric which provides a route to building reconfigurable spin-based Logic circuits compatible with conventional electron-based devices. A distinctive feature of the proposed NanoFabric is that a bit of information is encoded into the phase of the spin wave signal. It makes possible to transmit information without the use of electric current and utilize wave interference for useful Logic functionality. The basic elements include voltage-to-spin wave and wave-to-voltage converters, spin waveguides, a modulator, and a magnetoelectric cell. As an example of a magnetoelectric cell, we consider a two-phase piezoelectric-piezomagnetic system, where the spin wave signal modulation is due to the stress-induced anisotropy caused by the applied electric field. The performance of the basic elements is illustrated by experimental data and results of numerical modeling. The combination of the basic elements let us construct magnetic circuits for NOT and Majority Logic gates. Logic gates AND, OR, NAND and NOR are shown to be constructed as the combination of NOT and a reconfigurable Majority gates. The examples of computational architectures such as Cellular Automata, Cellular Nonlinear Network and Field Programmable Gate Array are described. The main advantage of the proposed NanoFabric is in the ability to realize Logic gates with less number of devices than it required for CMOS-based circuits. Potentially, the area of the elementary reconfigurable Majority gate can be scaled down to 0.1um2. The disadvantages and limitations of the proposed NanoFabric are discussed.
Emanuele Orgiu - One of the best experts on this subject based on the ideXlab platform.
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Boosting and Balancing Electron and Hole Mobility in Single- and Bilayer WSe2 Devices via Tailored Molecular Functionalization.
ACS nano, 2019Co-Authors: Marc-antoine Stoeckel, Marco Gobbi, Tim Leydecker, Ye Wang, Matilde Eredia, Sara Bonacchi, Roberto Verucchi, Melanie Timpel, Marco Vittorio Nardi, Emanuele OrgiuAbstract:WSe2 is a layered ambipolar semiconductor enabling hole and electron transport, which renders it a suitable active component for Logic Circuitry. However, solid-state devices based on single- and b...
Y. Suzuki - One of the best experts on this subject based on the ideXlab platform.
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Asynchronous High-Speed Combination Logic Circuitry using LTPS-TFT and BST for LCD Panel
2008 International Symposium on Communications and Information Technologies, 2008Co-Authors: T. Sato, Y. Suzuki, Y. SugaAbstract:In this paper, an asynchronous high-speed Logic Circuitry using low temperature poly silicon-thin film transistor (LTPS-TFT) and the bootstrapped technology (BST) for liquid crystal display (LCD) is proposed. The proposed Logic circuit operates at high frequency region owing to the deep non-saturation operation by using the bootstrapped technology. To confirm some characteristics of the proposed circuit, an inverter and a NAND gate circuits are simulated. As the results, the power delay products are about 1/3 times less value than that of the conventional circuit under the conditions of +10 V power supply voltage and 0.5 pF load capacitor.
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High-Speed Logic Circuitry Using Bootstrapped and Low-Temperature Polysilicon (LTPS) Technologies for TFT-LCD Panels
IEICE Transactions on Electronics, 2006Co-Authors: Y. Suzuki, Kazuhide IshikawaAbstract:In this paper, a high-speed Logic Circuitry using bootstrapped and low-temperature polysilicon (LTPS) technologies for TFT-LCD panels is proposed. The new Circuitry realizes high-speed operation owing to the application of a Logic-swing voltage that is wider than the power-supply voltage using bootstrapped technology. As a result, the new Logic Circuitry can be operated at an operational frequency around 3-10 times higher than that of the conventional Circuitry under the conditions of a 0.5 pF load capacitor at the output of a noninverting buffer and +10 V power-supply voltages. The new circuit is named "BST-TFT Logic Circuitry."
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High-speed Logic Circuitry used bootstrapped technology and low-temperature poly-silicon technology for TFT-LCD panel
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems 2004. Proceedings., 1Co-Authors: K. Matsunaga, Y. Suzuki, K. UmedaAbstract:In this paper, a high-speed Logic Circuitry used bootstrapped technology and Low Temperature Poly Silicon (LTPS) technology for TFT- LCD panel is proposed. The high-speed Logic Circuitry realizes the high-speed operation due to applying the wider swing-voltage than the power-supply voltage by using the bootstrapped technology. As the results, the new Logic Circuitry can operate at the operational frequency by around 10 times than the conventional Circuitry under the conditions of 0.5pF load-capacitor and +1OV power-supply voltages.
Tsutomu Yoshihara - One of the best experts on this subject based on the ideXlab platform.
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Self-Compensating Power Supply Circuit for Low Voltage SOI
2007 International Conference on Communications Circuits and Systems, 2007Co-Authors: Leona Okamura, Fukashi Morishita, Katsumi Dosaka, Kazutami Arimoto, Tsutomu YoshiharaAbstract:SOI device is promised to be a mobile and wireless network applications as it has better potential of high speed, low operating voltage and Q-factor. Gate Body directly connected SOI MOSFET suppresses Sees historical effects and is promised technologies that let the Logic Circuitry work in ultra low voltage. Compared to Bulk-Si MOSFET, GBSOI can reduce its power supply voltage by 30%, its current by 26% and its power dissipation by 47%. However sub-Gbps level clocking circuits with ultra low voltage require the smaller PVT (process, voltage and temperature) variation. This paper presents an architecture to stabilize SOI Logic Circuitry against PVT variation especially under ultra low power supply voltage. Deviation of gate delay caused by PVT variation is reduced to 1.6%, while 40% with Bulk-Si. This system realizes the cell libraries whose gate delay is constant despite PVT variation. They greatly help designing Circuitry especially under ultra low voltage.
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An Automatic Source/Body Level Controllable 0.5V level SOI Circuit Technique for Mobile and Wireless Network Applications
2006 International Symposium on Communications and Information Technologies, 2006Co-Authors: Leona Okamura, Fukashi Morishita, Katsumi Dosaka, Kazutami Arimoto, Tsutomu YoshiharaAbstract:SOI device has the better potential of high speed, low operating voltage and RF functions like as mobile and wireless network applications. Gate Body directly connected SOI MOSFET without historical effects is one of the promised technologies that let the Logic Circuitry work in ultra low voltage. Compared to Bulk-Si MOSFET, GBSOI can reduce its power supply voltage by 30%, its current by 26% and its power dissipation by 47%. However sub-Gbps level clocking circuits with ultra low voltage require the smaller PVT (process, voltage and temperature) variation. This paper presents an architecture to stabilize SOI Logic Circuitry against PVT variation especially under ultra low power supply voltage. Deviation of gate delay caused by PVT variation is reduced to 1.6%, while 40% with Bulk-Si. This system realizes the cell libraries whose gate delay is constant despite PVT variation. They greatly help designing Circuitry especially under ultra low voltage.
