The Experts below are selected from a list of 5574 Experts worldwide ranked by ideXlab platform
D Williams - One of the best experts on this subject based on the ideXlab platform.
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ITC - System Manufacturing Test cost model
Proceedings. International Test Conference, 2002Co-Authors: D Williams, Anthony P. AmblerAbstract:This paper proposes a Manufacturing Test cost model for systems as they go through a Manufacturing Test process. The cost model allows the company to calibrate the Test process to the risks of the product, while taking into account other Manufacturing and development processes. Without an accurate cost model, understanding the financial implications of Test tradeoffs is impossible.
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system Manufacturing Test cost model
International Test Conference, 2002Co-Authors: D Williams, Anthony P. AmblerAbstract:This paper proposes a Manufacturing Test cost model for systems as they go through a Manufacturing Test process. The cost model allows the company to calibrate the Test process to the risks of the product, while taking into account other Manufacturing and development processes. Without an accurate cost model, understanding the financial implications of Test tradeoffs is impossible.
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ITC - PC Manufacturing Test in a high volume environment
International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034), 1999Co-Authors: D WilliamsAbstract:This paper will introduce the reader to a wide range of issues related to choosing and implementing the proper Manufacturing Test philosophy for a given situation. The issues which need to be understood when formulating a Manufacturing Test philosophy are the Manufacturing environment, the customer's requirements, the fault spectrum of interest, and the relative strengths and weaknesses of different system Testing schemes. This paper will then look at Dell specifically and toward future issues affecting Manufacturing of PCs.
M.m.v. Tegethoff - One of the best experts on this subject based on the ideXlab platform.
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IC Manufacturing Test cost estimation at early stages of the design cycle
Microelectronics Journal, 1999Co-Authors: Thomas M. Chen, Kim Von-kyoung, M.m.v. TegethoffAbstract:This article presents a Test cost prediction model as a planning tool at an early stage of the design cycle to estimate Manufacturing Test cost of ICs. The proposed cost model estimates the IC Manufacturing Test cost based on Test throughput. The model calculates Test throughput by incorporating IC yield and fault coverage. Chip Manufacturing information was used to predict the Test cost and Test quality in IC Manufacturing Test. The objective of the cost model is to better plan IC product design and reduce cost by predicting the IC Manufacturing Test cost at an early stage of the design cycle without relying on detailed information such as layout or even netlist. The proposed model was applied to a commercial ASIC product. The model estimation result showed an acceptable accuracy as a first order approximation tool.
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ITC - ASIC Manufacturing Test cost prediction at early design stage
Proceedings International Test Conference 1997, 1997Co-Authors: Thomas M. Chen, M.m.v. TegethoffAbstract:This paper proposes a rest cost prediction model which estimates the cost of lC Testing in a Manufacturing environment. The model predicts chip Testing cost and quality of Test using a set of circuit Manufacturing parameters. The objective is to use these circuit parameters which are available at the early stage of the design cycle to determine and optimize Manufacturing Test cost.
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Simulation Techniques for the Manufacturing Test of MCMs
Journal of Electronic Testing, 1997Co-Authors: M.m.v. Tegethoff, Thomas M. ChenAbstract:Simulation techniques used in the Manufacturing Test SIMulator (MTSIM) are described. MTSIM is a Concurrent Engineering tool used to simulate the Manufacturing Test and repair aspects of boards and MCMs from design concept through Manufacturing release. MTSIM helps designers select assembly process, specify Design For Test (DFT) features, select board Test coverage, specify ASIC defect level goals, establish product feasibility, and predict Manufacturing quality and cost goals. A new yield model for boards and MCMs which accounts for the clustering of solder defects is introduced and used to predict the yield at each Test step. In addition, MTSIM estimates the average number of defects per board detected at each Test step, and estimates costs incurred in Test execution, fault isolation and repair. MTSIM models were validated with high performance assemblies at Hewlett-Packard (HP).
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ITC - Manufacturing Test simulator: a concurrent engineering tool for boards and MCMs
Proceedings. International Test Conference, 1994Co-Authors: M.m.v. Tegethoff, Thomas M. ChenAbstract:A board and multi-chip module (MCM) Manufacturing Test simulator (MTSIM) is described, MTSIM is a concurrent engineering tool used to simulate the Manufacturing Test and repair aspects of boards and MCMs from design concept through Manufacturing release. MTSIM helps designers select assembly process, specify, design for Test (DFT) features, select board Test coverage specify ASIC defect level goals, establish product feasibility, and predict Manufacturing quality and cost goals. MTSIM was implemented in the Mentor Graphics Falcon framework at Colorado State University (CSU) and validated with high performance assemblies at Hewlett-Packard (HP). MTSIM is a step towards the simulation of the whole board/MCM assembly factory.
Anthony P. Ambler - One of the best experts on this subject based on the ideXlab platform.
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ITC - System Manufacturing Test cost model
Proceedings. International Test Conference, 2002Co-Authors: D Williams, Anthony P. AmblerAbstract:This paper proposes a Manufacturing Test cost model for systems as they go through a Manufacturing Test process. The cost model allows the company to calibrate the Test process to the risks of the product, while taking into account other Manufacturing and development processes. Without an accurate cost model, understanding the financial implications of Test tradeoffs is impossible.
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system Manufacturing Test cost model
International Test Conference, 2002Co-Authors: D Williams, Anthony P. AmblerAbstract:This paper proposes a Manufacturing Test cost model for systems as they go through a Manufacturing Test process. The cost model allows the company to calibrate the Test process to the risks of the product, while taking into account other Manufacturing and development processes. Without an accurate cost model, understanding the financial implications of Test tradeoffs is impossible.
Yves Joannon - One of the best experts on this subject based on the ideXlab platform.
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Decreasing Test Qualification Time of AMS&RF Systems by using Normal Estimation
IEEE Design & Test, 2008Co-Authors: Yves Joannon, Vincent Beroulle, Chantal Robach, Smail Tedjini, J.l. CarboneroAbstract:The Test cost of heterogeneous integrated circuits has significantly increased. So, the definition of relevant Test methods and efficient Test stimuli are becoming crucial research orientations for semiconductor manufacturers. In this paper, we propose to decrease the Manufacturing Test cost of AMS&RF System-on-Chips (SoC) by automatically qualifying and optimizing existing Test set. We will present a Computed Aided Test tool PLASMA that uses faults injection and faults simulation technique to perform the Test qualification and generation. This tool reduces both Test time and Test equipments cost using a high-level fault model. After discussing on the advantages of the choice of behavioral faults models, we present a method that allows us to decrease the overall simulation times. This method proposes to reduce the number of simulated fault-free models thanks to a normal estimation.
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Choice of a high level fault model for the Optimization of Validation Test Set reused for Manufacturing Test
IEEE International Mixed-Signals Testing Workhop (IMSTW 07), 2007Co-Authors: Yves Joannon, Vincent Beroulle, Chantal Robach, Smail Tedjini, Jean-louis CarboneroAbstract:With the growing complexity of Wireless Systems on Chip integrating hundred-of-million transistors, electronic design methods need to be upgraded to reduce time-to-market. In this paper, the Test benches defined for design validation or characterization of AMS & RF SoCs are optimized and re-used for production Testing. Although the original validation Test set allows the verification of both design functionalities and performances, this Test set is not well adapted to Manufacturing Test due to its high execution time and high Test equipments costs requirement. The optimization of this validation Test set is based on the evaluation of each Test vector. This evaluation relies on high level fault modeling and fault simulation. Hence, a fault model based on the variations of the parameters of high abstraction level descriptions and its related qualification metric are presented. The choice of functional or behavioral abstraction levels is discussed by comparing their impact on structural fault coverage. Experiments are performed on the receiver part of a WCDMA transceiver. Results show that for this SoC, using behavioral abstraction level is justified for the generation of Manufacturing Test benches.
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Using of Behavioral level AMS & RF Simulation for Validation Test Set Optimization
IEEE Wireless Test Workhop (WTW07), 2007Co-Authors: Yves Joannon, Vincent Beroulle, Chantal Robach, Smail Tedjini, Jean-louis CarboneroAbstract:The expansion of Wireless Systems-on-Chip leads to a rapid development of new design and Test methods. In this paper, the Test benches defined for design validation or characterization of AMS & RF SoCs are first optimized and then re-used for production Testing. Although the original validation Test set allows the verification of both design functionalities and performances, this Test set is not well adapted to Manufacturing Test due to its high execution time and high Test equipments costs requirement. The optimization of this validation set is based on the evaluation of each Test stimuli. This evaluation relies on a high level faults simulation method. Hence, a fault model based on the variations of behavioral parameters and its related qualification metric are presented. This approach is used on the receiver part of a WCDMA transceiver. The Test bench optimization realized is evaluated for Manufacturing Test thanks to structural fault coverage measurements.
Thomas M. Chen - One of the best experts on this subject based on the ideXlab platform.
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IC Manufacturing Test cost estimation at early stages of the design cycle
Microelectronics Journal, 1999Co-Authors: Thomas M. Chen, Kim Von-kyoung, M.m.v. TegethoffAbstract:This article presents a Test cost prediction model as a planning tool at an early stage of the design cycle to estimate Manufacturing Test cost of ICs. The proposed cost model estimates the IC Manufacturing Test cost based on Test throughput. The model calculates Test throughput by incorporating IC yield and fault coverage. Chip Manufacturing information was used to predict the Test cost and Test quality in IC Manufacturing Test. The objective of the cost model is to better plan IC product design and reduce cost by predicting the IC Manufacturing Test cost at an early stage of the design cycle without relying on detailed information such as layout or even netlist. The proposed model was applied to a commercial ASIC product. The model estimation result showed an acceptable accuracy as a first order approximation tool.
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ITC - ASIC Manufacturing Test cost prediction at early design stage
Proceedings International Test Conference 1997, 1997Co-Authors: Thomas M. Chen, M.m.v. TegethoffAbstract:This paper proposes a rest cost prediction model which estimates the cost of lC Testing in a Manufacturing environment. The model predicts chip Testing cost and quality of Test using a set of circuit Manufacturing parameters. The objective is to use these circuit parameters which are available at the early stage of the design cycle to determine and optimize Manufacturing Test cost.
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Simulation Techniques for the Manufacturing Test of MCMs
Journal of Electronic Testing, 1997Co-Authors: M.m.v. Tegethoff, Thomas M. ChenAbstract:Simulation techniques used in the Manufacturing Test SIMulator (MTSIM) are described. MTSIM is a Concurrent Engineering tool used to simulate the Manufacturing Test and repair aspects of boards and MCMs from design concept through Manufacturing release. MTSIM helps designers select assembly process, specify Design For Test (DFT) features, select board Test coverage, specify ASIC defect level goals, establish product feasibility, and predict Manufacturing quality and cost goals. A new yield model for boards and MCMs which accounts for the clustering of solder defects is introduced and used to predict the yield at each Test step. In addition, MTSIM estimates the average number of defects per board detected at each Test step, and estimates costs incurred in Test execution, fault isolation and repair. MTSIM models were validated with high performance assemblies at Hewlett-Packard (HP).
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ITC - Manufacturing Test simulator: a concurrent engineering tool for boards and MCMs
Proceedings. International Test Conference, 1994Co-Authors: M.m.v. Tegethoff, Thomas M. ChenAbstract:A board and multi-chip module (MCM) Manufacturing Test simulator (MTSIM) is described, MTSIM is a concurrent engineering tool used to simulate the Manufacturing Test and repair aspects of boards and MCMs from design concept through Manufacturing release. MTSIM helps designers select assembly process, specify, design for Test (DFT) features, select board Test coverage specify ASIC defect level goals, establish product feasibility, and predict Manufacturing quality and cost goals. MTSIM was implemented in the Mentor Graphics Falcon framework at Colorado State University (CSU) and validated with high performance assemblies at Hewlett-Packard (HP). MTSIM is a step towards the simulation of the whole board/MCM assembly factory.
