The Experts below are selected from a list of 222 Experts worldwide ranked by ideXlab platform

H. Koch - One of the best experts on this subject based on the ideXlab platform.

  • A 2-channel wideband SQUID system for high-frequency geophysical applications
    IEEE Transactions on Applied Superconductivity, 1997
    Co-Authors: D. Drung, H. Matz, T. Radic, S. Knappe, S. Menkel, H. Koch, H. Burkhardt
    Abstract:

    A prototype radiomagnetic sounding system for measuring the conductivity of the shallow subsoil down to some 10 m depth was built. With this system, the horizontal magnetic field and field gradient of radio transmitters in the frequency range 10-2000 kHz are detected in small bore-holes of /spl lsim/1 m depth using two wideband SQUIDs. The SQUIDs are opeRated at 4.2 K in a flux-locked loop having a bandwidth of 11 MHz, a white flux noise level of 1.6/spl times/10/sup -6/ /spl Phi//sub 0///spl radic/(Hz), a feedback range of /spl plusmn/610 /spl Phi//sub 0/, and a Maximum Slew Rate of 2/spl times/10/sup 6/ /spl Phi//sub 0//s above 500 kHz increasing to 5/spl times/10/sup 7/ /spl Phi//sub 0//s at 13 kHz. The system was successfully tested in a first field measurement under urban environmental conditions. The system design allows one in principle to use nitrogen-cooled sensors.

  • Practical low‐noise integRated dc superconducting quantum interference device magnetometer with additional positive feedback
    Applied Physics Letters, 1991
    Co-Authors: Tapani Ryhänen, Dietmar Drung, R. Cantor, H. Koch
    Abstract:

    We have designed and fabricated a low‐noise dc superconducting quantum interference device (SQUID) magnetometer that is integRated on a 4×4 mm2 chip. The white flux noise of the magnetometer measured in a flux‐locked‐loop mode using simple, direct‐coupled electronics with additional positive feedback (APF) is 6.4×10−7 Φ0/√Hz. The corresponding white flux density noise is 3.9 fT/√Hz. The SQUID flux‐to‐voltage transfer function with APF is enhanced to 4.7 mV/Φ0 at the optimal working point, thereby significantly reducing the preamplifier contribution to the total noise. A Maximum feedback field of 65 nT for frequencies up to 300 Hz and a Maximum Slew Rate of 120 μT/s at 300 Hz have been attained using a two‐pole integrator.

Hsin-yuan Tseng - One of the best experts on this subject based on the ideXlab platform.

  • Process corner detection by skew inverters for 500 MHZ 2×VDD output buffer using 40-nm CMOS technology
    Microelectronics Journal, 2015
    Co-Authors: Chua-chin Wang, Kai-wei Juan, Wei Lin, Hsin-yuan Tseng, Chun-ying Juan
    Abstract:

    Abstract A PVT detection and compensation technique is proposed to automatically adjust the Slew Rate of a high-speed 2×VDD output buffer. Based on the detected PVT (Process, Voltage, Temperature) corner, the output buffer will turn on different current paths correspondingly to either increase or decrease the output driving current such that the Slew Rate of the output signal is adaptive. The proposed design is implemented using a typical 40 nm CMOS process to justify the Slew Rate compensation performance. By on-silicon measurements, the data Rate is 500/460 MHz given 0.9/1.8 V supply voltage with a 20 pF load. Particularly, the Maximum Slew Rate improvement is 8%, the core area of the proposed design is 0.052×0.254 mm2, the Maximum Slew Rate is 0.53 (V/ns), and the area overhead is only 31% for one single output buffer.

  • ISCAS - A high-speed 2×VDD output buffer with PVT detection using 40-nm CMOS technology
    2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
    Co-Authors: Chua-chin Wang, Hsin-yuan Tseng
    Abstract:

    A high-speed compensation technique is proposed to automatically adjust the Slew Rate of a 2×VDD output buffer. Based on the detected PVT (Process, Voltage, Temperature) corner, the output buffer will turn on different current paths correspondingly to either increase or decrease the output driving current such that the Slew Rate of the output can be adjusted as well. The proposed design is implemented using a typical 40 nm CMOS process to justify the Slew Rate compensation performance. By on-silicon measurements, the data Rate is 500/460 MHz given 0.9/1.8 V supply voltage with a 20 pF load, the Maximum Slew Rate is 0.53 (V/ns), and the core area of the proposed design is 0.052 × 0.254 mm2.

  • A 2íVDD output buffer with PVT detector for Slew Rate compensation
    Microelectronics Journal, 2013
    Co-Authors: Chua-chin Wang, Hsin-yuan Tseng, Chih-lin Chen, Ron-chi Kuo, Chun-ying Juan
    Abstract:

    A novel PVT (process, voltage, temperature) detection and compensation technique is proposed to automatically adjust the Slew Rate of a 2xVDD output buffer. The threshold voltage (Vth) of PMOSs and NMOSs varying with process, supply voltage, and temperature (PVT) is detected, respectively. Based on the detected PVT corner, the output buffer will turn on different current paths correspondingly to either increase or decrease the output driving current such that the Slew Rate of the output can be adjusted as well. The proposed design is implemented using a typical 90nm CMOS process to justify the Slew Rate performance. By the on-silicon measurements, the Slew Rate of output signal is compensated over 26%, the Maximum Slew Rate is 1.65 (V/ns), the Maximum data Rate is 330MHz given 1.2/0.9V supply voltage with a 20pF load, the core area of the proposed design is 0.056x0.406mm^2, and the power consumption is 2.2mW at 330MHz data Rate.

Chua-chin Wang - One of the best experts on this subject based on the ideXlab platform.

  • Process corner detection by skew inverters for 500 MHZ 2×VDD output buffer using 40-nm CMOS technology
    Microelectronics Journal, 2015
    Co-Authors: Chua-chin Wang, Kai-wei Juan, Wei Lin, Hsin-yuan Tseng, Chun-ying Juan
    Abstract:

    Abstract A PVT detection and compensation technique is proposed to automatically adjust the Slew Rate of a high-speed 2×VDD output buffer. Based on the detected PVT (Process, Voltage, Temperature) corner, the output buffer will turn on different current paths correspondingly to either increase or decrease the output driving current such that the Slew Rate of the output signal is adaptive. The proposed design is implemented using a typical 40 nm CMOS process to justify the Slew Rate compensation performance. By on-silicon measurements, the data Rate is 500/460 MHz given 0.9/1.8 V supply voltage with a 20 pF load. Particularly, the Maximum Slew Rate improvement is 8%, the core area of the proposed design is 0.052×0.254 mm2, the Maximum Slew Rate is 0.53 (V/ns), and the area overhead is only 31% for one single output buffer.

  • ICICDT - A high-speed 2×VDD output buffer with PVTL detection using 40-nm CMOS technology
    2015 International Conference on IC Design & Technology (ICICDT), 2015
    Co-Authors: Chua-chin Wang, Tsung-yi Tsai, Wei Lin
    Abstract:

    Not only PVT detection techniques but also a leakage compensation design are proposed to carry out 650/500 MHz 2×VDD output buffer in this paper. The proposed 2×VDD output buffer contains a novel PVTL (Process, Voltage, Temperature, Leakage) compensation circuit to resolve the problems in output buffers of nano-scale CMOS technologies. Particularly, the leakage compensation design is realized by an asynchronous control method to control current paths such that the switching loss and the Slew Rate in the output buffer can be reduced and increased, respectively. The proposed design has been realized and implemented by using a typical 40 nm CMOS process. The data Rate is 650/500 MHz given 0.9/1.8 V supply voltage with a 20 pF load. The Maximum Slew Rate is 3.5 (V/ns), and the core area is 0.052 × 0.213 mm2.

  • ISCAS - A high-speed 2×VDD output buffer with PVT detection using 40-nm CMOS technology
    2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
    Co-Authors: Chua-chin Wang, Hsin-yuan Tseng
    Abstract:

    A high-speed compensation technique is proposed to automatically adjust the Slew Rate of a 2×VDD output buffer. Based on the detected PVT (Process, Voltage, Temperature) corner, the output buffer will turn on different current paths correspondingly to either increase or decrease the output driving current such that the Slew Rate of the output can be adjusted as well. The proposed design is implemented using a typical 40 nm CMOS process to justify the Slew Rate compensation performance. By on-silicon measurements, the data Rate is 500/460 MHz given 0.9/1.8 V supply voltage with a 20 pF load, the Maximum Slew Rate is 0.53 (V/ns), and the core area of the proposed design is 0.052 × 0.254 mm2.

  • A 2íVDD output buffer with PVT detector for Slew Rate compensation
    Microelectronics Journal, 2013
    Co-Authors: Chua-chin Wang, Hsin-yuan Tseng, Chih-lin Chen, Ron-chi Kuo, Chun-ying Juan
    Abstract:

    A novel PVT (process, voltage, temperature) detection and compensation technique is proposed to automatically adjust the Slew Rate of a 2xVDD output buffer. The threshold voltage (Vth) of PMOSs and NMOSs varying with process, supply voltage, and temperature (PVT) is detected, respectively. Based on the detected PVT corner, the output buffer will turn on different current paths correspondingly to either increase or decrease the output driving current such that the Slew Rate of the output can be adjusted as well. The proposed design is implemented using a typical 90nm CMOS process to justify the Slew Rate performance. By the on-silicon measurements, the Slew Rate of output signal is compensated over 26%, the Maximum Slew Rate is 1.65 (V/ns), the Maximum data Rate is 330MHz given 1.2/0.9V supply voltage with a 20pF load, the core area of the proposed design is 0.056x0.406mm^2, and the power consumption is 2.2mW at 330MHz data Rate.

Anna V. Bugakova - One of the best experts on this subject based on the ideXlab platform.

  • ICSTCC - Mathematical Analysis of Transients of the High-Speed Buffer Amplifier with the Complementary Composite Transistors in Nonlinear Mode
    2019 23rd International Conference on System Theory Control and Computing (ICSTCC), 2019
    Co-Authors: Nikolay N. Prokopenko, Anna V. Bugakova, A. R. Gaiduk, Elena V. Ovsepian
    Abstract:

    The analysis of transients of the suggested butter amplifier (BA) with the complementary composite transistors containing special differentiation correction circuits (DCC) is performed. The mathematical analyses of the limit values of the Maximum Slew Rate of the out voltage and time transient of this class BA in nonlinear mode is given. The results of computer simulation of the BA in PSpice environment on the models of typical integRated bipolar transistors are given. This results show that due to the application of the DCC, the time transient of the BA is reduced by ten folds up to several nanoseconds. The proposed BA is recommended to be used in control and automatic control systems where amplifiers with low current consumption are required.

  • the differentiating correction circuits in complementary buffer amplifiers
    International Conference of Young Specialists on Micro Nanotechnologies and Electron Devices, 2018
    Co-Authors: Nikolay N. Prokopenko, Anna V. Bugakova, Andrey A Ignashyn, Elena V Ovsepyan
    Abstract:

    _ It is shown that the performance of the ICs of complementary buffer amplifiers (BA) widely used as drivers of cable communication lines in devices of radio engineering and telecommunications is significantly influenced by parasitic capacitances (C p1 , C p2 ) in the emitter circuits of the input voltage followers and reduced to the load capacitance C p1 (C p2 ). This limits the Maximum Slew Rate (SR), which becomes small at the BA low power consumption in the static mode. The authors propose a method for the SR increasing in the micro-power BAs by introducing special differentiating circuits into the BA classical scheme for the transient correction. It is established that the recommended options of differentiating capacitor connections allow the generation of additional recharge currents of parasitic capacitances C p1 (C p2 ), thus improving the SR and reducing the transient time. The results of computer simulation of the BA for BJT of the complementary technological process of JCT “SPE Pulsar” (Moscow), and also on the transistors of the analogue array chip ABMK_1.7, show that the SR of complementary BA increases more than 10 times to 20000 V/°s (at a current of consumption Ip = 500 °A, including when operating in the low temperature range and exposure to radiation.

  • The Non-Linear Differentiating Circuits of Correction of Transient Process in Differential Operational Amplifiers
    2018 19th International Conference of Young Specialists on Micro Nanotechnologies and Electron Devices (EDM), 2018
    Co-Authors: Nikolaevich Nikolaj Prokopenko, Anna V. Bugakova, Aleksandr I. Serebryakov
    Abstract:

    The nonlinear equivalent circuits for small and large signals of the input circuits of the classical BJT operational amplifier (Op-Amp), which relates to the basic functional nodes of analog-digital interfaces of modern automatic control systems and it has a significant effect on some of their dynamic parameters, are discussed. This enabled us to formulate a circuit method for connecting a differentiating correction circuit (DCC) of the transient to the standard Op-Amp. Such solution reduces significantly the recharging time of the Op-Amp integrating capacitor (Cc1), which forms the given phase margin and the unity gain frequency. It is shown that, on a small signal, the additional differentiating capacitor Cc2has practically no effect on the Op-Amp operation; however, it increases the Maximum Slew Rate (SR) at the dynamic overload of the main Op-Amp input stage. The estimates of the SR limiting values are given with regard to the lag effect of the main Op-Amp functional nodes. The proposed method of connecting a differentiating correction circuit effectively works both in the Op-Amps and in other electronic devices of automation and robotics (continuous voltage stabilizers with differential stages, comparators, etc., implemented by modern technological processes - BJT, BiJFet, SiGe, CMOS, SOI, SOS, etc.).

  • The Comparative Analysis of the Maximum Slew Rate of the Output Voltage BJT and CMOS (SiGe TSMC 0.35µ) Operational Amplifiers
    2018 19th International Conference of Young Specialists on Micro Nanotechnologies and Electron Devices (EDM), 2018
    Co-Authors: Nikolay N. Prokopenko, Nikolay V. Butyrlagin, Anna V. Bugakova
    Abstract:

    The authors compare two options for constructing operational amplifiers (Op-Amp) with a classical two-stage architecture on the Maximum Slew Rate (SR) used in electronic devices of automatics (EDA) and robotics when implemented in the framework of BJT and CMOS technologies. The analysis is carried out for the case when the transfer function of the Op-Amp open-loop gain is described by the first-order lag. It is established that for typical Op-Amps on bipolar transistors the SR doesn't practically change over a wide range of static currents of the standard input differential stage (DS), which (in most cases) performs the role of the correction capacitance driver DCc (C c ). It is shown that the CMOS Op-Amps have substantially comprehensive facilities, in which the SR can exceed the SR of similar BJT Op-Amps by several tens of times. However, when the input stages of the compared BJT and CMOS Op-Amps opeRate in microregime, their high-speed response (at identical unity gain frequencies) is approximately the same. A comparative analysis of two formulas used in the theory of the EDA for the estimation of SR, which enables to determine the limits to their applicability and clarify the recommendations for constructing the high-speed Op-Amps for hardware tasks of robotic and mechatronic systems.

  • Features of Increasing the Fast Response of Differential Operational Amplifiers on the Basis of a "Folded" Cascode
    2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 2018
    Co-Authors: Nikolay N. Prokopenko, Anna V. Bugakova, Alexey E. Titov, Petr S. Budyakov
    Abstract:

    New and prospective circuit techniques for increasing the fast response of operational amplifiers (Op-Amps) containing the so-called "folded" cascode in the structure of an intermediate stage (IC) are considered. It is shown that under the constraints on power consumption in the static mode, the classical solutions of the Op-Amp of this subclass can not provide increased values of the Maximum Slew Rate (SR) due to the nonlinearity of the transfer characteristic of the FC. Comparison of the methods for excluding the limitations of the output current of the "folded" cascode is given. Perspective architecture of high-speed micro-power Op-Amps with a differentiating correction circuit is proposed, which enables to increase the SR by 1-2 orders, incl. when working in the low temperature range and under conditions of penetrating radiation.

L. Wozniak - One of the best experts on this subject based on the ideXlab platform.

  • Maximum Slew-Rate governor control for impulse turbines
    IEEE Transactions on Energy Conversion, 1991
    Co-Authors: R. Erickson, L. Wozniak
    Abstract:

    A deflector bang-bang and speed derivative methodology for controlling impulse turbine transients is developed. The control was implemented in a linear simulation to demonstRate its effectiveness in controlling load torque perturbations. The proposed controller stRategy is implemented in a nonlinear simulation. The design was found to significantly reduce turbine off-speeds and nominal operating point settling times in both simulations. >