The Experts below are selected from a list of 186 Experts worldwide ranked by ideXlab platform
Mingdou Ker - One of the best experts on this subject based on the ideXlab platform.
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Power Rail esd clamp circuit with polysilicon diodes against false trigger during fast Power on events
Electrical Overstress Electrostatic Discharge Symposium, 2018Co-Authors: Jieting Chen, Mingdou KerAbstract:A new Power-Rail ESD clamp circuit with both timing and voltage-level detection is proposed against false trigger events. A RC stage is used for dv/dt detection and a diode string is used to detect the over-stress voltage level during ESD events. By using fully isolated polysilicon diodes, the standby leakage current of the proposed Power-Rail ESD clamp can be effectively reduced.
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ESD Failure Mechanisms of Analog I/O Cells
2016Co-Authors: Mingdou Ker, Shihhung Chen, Senior Member, Che-hao ChuangAbstract:Abstract—Different electrostatic discharge (ESD) protection schemes have been investigated to find the optimal ESD protec-tion design for an analog input/output (I/O) buffer in 0.18-µm 1.8- and 3.3-V CMOS technology. Three Power-Rail ESD clamp devices were used in Power-Rail ESD clamp circuits to com-pare the protection efficiency in analog I/O applications, namely: 1) gate-driven NMOS; 2) substrate-triggered field-oxide device, and 3) substrate-triggered NMOS with dummy gate. From the experimental results, the pure-diode ESD protection devices and the Power-Rail ESD clamp circuit with gate-driven NMOS are the suitable designs for the analog I/O buffer in the 0.18-µm CMOS process. Each ESD failure mechanism was inspected by scanning electron microscopy photograph in all the analog I/O pins. An unexpected failure mechanism was found in the analog I/O pins with pure-diode ESD protection design under ND-mode ESD stress. The parasitic n-p-n bipolar transistor between the ESD clamp device and the guard ring structure was triggered to discharge the ESD current and cause damage under ND-mode ESD stress. Index Terms—Analog I/O, electrostatic discharge (ESD), failure mechanism, input/output (I/O) cell, Power-Rail ESD clamp device. I
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area efficient esd clamp circuit with a capacitance boosting technique to minimize standby leakage current
IEEE Transactions on Device and Materials Reliability, 2015Co-Authors: Federico A Altolaguirre, Mingdou KerAbstract:This paper presents a new RC-based Power-Rail electrostatic discharge (ESD) clamp circuit, which achieves ultra-low leakage current while maintaining low silicon utilization. A capacitance-boosting technique is used in conjunction with mathematical analysis of area utilization to determine the best set of parameters to achieve the smallest implementation area in silicon. The proposed Power-Rail ESD clamp circuit has been verified in a 65-nm general-purpose CMOS process, which achieves an ultra-low standby leakage current of 80 nA at 25 °C under 1-V bias, as well as ESD robustness of a 4-kV human body model and a 250-V machine model with a silicon area of only $\mbox{45}\ \mu\mbox{m}\times \mbox{17}\ \mu\mbox{m}$ .
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on the design of Power Rail esd clamp circuits with gate leakage consideration in nanoscale cmos technology
IEEE Transactions on Device and Materials Reliability, 2014Co-Authors: Mingdou Ker, Chihting YehAbstract:CMOS technology has been widely used to produce many integrated circuits. However, the thinner gate oxide in nanoscale CMOS technology seriously increases the difficulty of electrostatic discharge (ESD) protection design. The Power-Rail ESD clamp circuit has been the key circuit to perform the whole-chip ESD protection scheme. Some ESD detection circuits were developed to trigger on ESD devices across the Power Rails to quickly discharge ESD current away from the internal circuits. Therefore, on-chip ESD protection circuits must be designed with the consideration of standby leakage to minimize the Power consumption and the possibility of malfunction to normal circuit operation. The design of Power-Rail ESD clamp circuits with low standby leakage current and high efficiency of layout area in nanoscale CMOS technology is reviewed in this paper. The comparisons among those Power-Rail ESD clamp circuits are also discussed.
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metal layer capacitors in the 65 nm cmos process and the application for low leakage Power Rail esd clamp circuit
Microelectronics Reliability, 2014Co-Authors: Poyen Chiu, Mingdou KerAbstract:Abstract Between the metal–insulator–metal (MIM) capacitor and metal–oxide–metal (MOM) capacitor, the MIM capacitor has a better characteristic of stable capacitance. However, the MOM capacitors can be easily realized through the metal interconnections, which does not need additional fabrication masks into the process. Moreover, the capacitance density of the MOM capacitor can exceed the MIM capacitor when more metal layers are used in nanoscale CMOS processes. With advantages of lower fabrication cost and higher capacitance density, the MOM capacitor could replace MIM capacitor gradually in general integrated circuit (IC) applications. Besides, the MOM capacitor ideally do not have the leakage issue. Thus, the MOM capacitor can be used instead of MOS capacitor to avoid the gate leakage issue of thin-oxide devices in nanoscale CMOS processes. With the MOM capacitor realized in the Power-Rail electrostatic discharge (ESD) clamp circuit, the overall leakage is decreased from 828 μA to 358 nA at 25 °C, as compared to the traditional design with MOS capacitor in the test chip fabricated in a 65 nm CMOS process.
Changtzu Wang - One of the best experts on this subject based on the ideXlab platform.
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design of 2 times vdd tolerant Power Rail esd clamp circuit with consideration of gate leakage current in 65 nm cmos technology
IEEE Transactions on Electron Devices, 2010Co-Authors: Changtzu WangAbstract:A low-leakage 2× VDD-tolerant Power-Rail electrostatic discharge (ESD) clamp circuit composed of the silicon-controlled rectifier (SCR) device and new ESD detection circuit, realized with only thin-oxide 1× VDD devices, has been proposed with consideration of gate leakage current. By reducing the voltage across the gate oxides of the devices in the ESD detection circuit, the whole Power-Rail ESD clamp circuit can achieve an ultralow standby leakage current. The new proposed circuit has successfully been verified in a 1-V 65-nm CMOS process, which can achieve 6.5-kV human-body-model and 350-V machine-model ESD levels under ESD stresses, but only consumes a standby leakage current of 0.15 μA at room temperature under normal circuit operating conditions with 1.8-V bias.
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design of Power Rail esd clamp circuit with ultra low standby leakage current in nanoscale cmos technology
IEEE Journal of Solid-state Circuits, 2009Co-Authors: Changtzu WangAbstract:An ultra-low-leakage Power-Rail ESD clamp circuit, composed of the SCR device and new ESD detection circuit, has been proposed with consideration of gate current to reduce the standby leakage current. By controlling the gate current of the devices in the ESD detection circuit under a specified bias condition, the whole Power-Rail ESD clamp circuit can achieve an ultra-low standby leakage current. The new proposed circuit has been fabricated in a 1 V 65 nm CMOS process for experimental verification. The new proposed Power-Rail ESD clamp circuit can achieve 7 kV HBM and 325 V MM ESD levels while consuming only a standby leakage current of 96 nA at 1 V bias in room temperature and occupying an active area of only 49 mum 21 mum.
Chihting Yeh - One of the best experts on this subject based on the ideXlab platform.
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on the design of Power Rail esd clamp circuits with gate leakage consideration in nanoscale cmos technology
IEEE Transactions on Device and Materials Reliability, 2014Co-Authors: Mingdou Ker, Chihting YehAbstract:CMOS technology has been widely used to produce many integrated circuits. However, the thinner gate oxide in nanoscale CMOS technology seriously increases the difficulty of electrostatic discharge (ESD) protection design. The Power-Rail ESD clamp circuit has been the key circuit to perform the whole-chip ESD protection scheme. Some ESD detection circuits were developed to trigger on ESD devices across the Power Rails to quickly discharge ESD current away from the internal circuits. Therefore, on-chip ESD protection circuits must be designed with the consideration of standby leakage to minimize the Power consumption and the possibility of malfunction to normal circuit operation. The design of Power-Rail ESD clamp circuits with low standby leakage current and high efficiency of layout area in nanoscale CMOS technology is reviewed in this paper. The comparisons among those Power-Rail ESD clamp circuits are also discussed.
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Power Rail esd clamp circuit with ultralow standby leakage current and high area efficiency in nanometer cmos technology
IEEE Transactions on Electron Devices, 2012Co-Authors: Chihting Yeh, Mingdou KerAbstract:An ultralow-leakage Power-Rail electrostatic discharge (ESD) clamp circuit realized with only thin gate oxide devices and with silicon-controlled rectifier (SCR) as the main ESD clamp device has been proposed and verified in a 65-nm CMOS process. By reducing the voltage difference across the gate oxide of the devices in the ESD detection circuit, the proposed Power-Rail ESD clamp circuit can achieve an ultralow standby leakage current. In addition, the ESD-transient detection circuit can be totally embedded in the SCR device by modifying the layout structure. From the measured results, the proposed Power-Rail ESD clamp circuit with an SCR width of 45 μm can achieve 7-kV human-body-model and 350-V machine-model ESD levels under the ESD stress event while consuming only a standby leakage current in the order of nanoamperes at room temperature under the normal circuit operating condition with 1-V bias.
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new design of 2 times vdd tolerant Power Rail esd clamp circuit for mixed voltage i o buffers in 65 nm cmos technology
IEEE Transactions on Circuits and Systems Ii-express Briefs, 2012Co-Authors: Chihting Yeh, Mingdou KerAbstract:A new 2 VDD-tolerant Power-Rail electrostatic discharge (ESD) clamp circuit realized with only thin gate oxide 1-V (1 VDD) devices and a silicon-controlled rectifier (SCR) as the main ESD clamp device has been proposed and verified in a 65-nm CMOS process. This new design has a low standby leakage current by reducing the voltage difference across the gate oxide of the devices in the ESD detection circuit. The proposed design with an SCR width of 50 can achieve a 6.5-kV human-body-model ESD level, a 300-V machine-model ESD level, and a low standby leakage current of only 103.7 nA at room temperature under the normal circuit operating condition with 1.8 V bias.
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pmos based Power Rail esd clamp circuit with adjustable holding voltage controlled by esd detection circuit
Electrical Overstress Electrostatic Discharge Symposium, 2011Co-Authors: Chihting Yeh, Yungchih Liang, Mingdou KerAbstract:A new Power-Rail ESD clamp circuit designed with PMOS as main ESD clamp device has been proposed and verified in a 65nm 1.2V CMOS process. The new proposed design with adjustable holding voltage controlled by the ESD detection circuit has better immunity against mis-trigger or transient-induced latch-on event. The layout area and the standby leakage current of this new proposed design are much superior to that of traditional RC-based Power-Rail ESD clamp circuit with NMOS as main ESD clamp device.
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design of Power Rail esd clamp circuit with adjustable holding voltage against mis trigger or transient induced latch on events
International Symposium on Circuits and Systems, 2011Co-Authors: Chihting Yeh, Yungchih Liang, Mingdou KerAbstract:In this work, a new design of the ESD-transient detection circuit with the n-channel metal-oxide-semiconductor (nMOS) transistor drawn in the layout style of big field-effect transistor (BigFET) has been proposed and verified in a 65nm 1.2V CMOS process. As compared to the traditional RC-based ESD-transient detection circuit, the layout area of the new ESD-transient detection circuit can be greatly reduced by more than 54%. From the experimental results, the new proposed ESD-transient detection circuit with adjustable holding voltage can achieve long turn-on duration under the ESD stress condition, as well as better immunity against mis-trigger or transient-induced latch-on event under the fast Power-on and transient noise conditions.
Federico A Altolaguirre - One of the best experts on this subject based on the ideXlab platform.
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area efficient esd clamp circuit with a capacitance boosting technique to minimize standby leakage current
IEEE Transactions on Device and Materials Reliability, 2015Co-Authors: Federico A Altolaguirre, Mingdou KerAbstract:This paper presents a new RC-based Power-Rail electrostatic discharge (ESD) clamp circuit, which achieves ultra-low leakage current while maintaining low silicon utilization. A capacitance-boosting technique is used in conjunction with mathematical analysis of area utilization to determine the best set of parameters to achieve the smallest implementation area in silicon. The proposed Power-Rail ESD clamp circuit has been verified in a 65-nm general-purpose CMOS process, which achieves an ultra-low standby leakage current of 80 nA at 25 °C under 1-V bias, as well as ESD robustness of a 4-kV human body model and a 250-V machine model with a silicon area of only $\mbox{45}\ \mu\mbox{m}\times \mbox{17}\ \mu\mbox{m}$ .
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Power Rail esd clamp circuit with diode string esd detection to overcome the gate leakage current in a 40 nm cmos process
IEEE Transactions on Electron Devices, 2013Co-Authors: Federico A AltolaguirreAbstract:A new silicon controlled rectifier-based Power-Rail electrostatic discharge (ESD) clamp circuit was proposed with a novel trigger circuit that has very low leakage current in a small layout area for implementation. This circuit was successfully verified in a 40-nm CMOS process by using only low-voltage devices. The novel trigger circuit uses a diode-string based level-sensing ESD detection circuit, but not using MOS capacitor, which has very large leakage current. Moreover, the leakage current on the ESD detection circuit is further reduced, adding a diode in series with the trigger transistor. By combining these two techniques, the total silicon area of the Power-Rail ESD clamp circuit can be reduced three times, whereas the leakage current is three orders of magnitude smaller than that of the traditional design.
Bernard H Stark - One of the best experts on this subject based on the ideXlab platform.
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a new design technique for sub nanosecond delay and 200 v ns Power supply slew tolerant floating voltage level shifters for gan smps
IEEE Transactions on Circuits and Systems I-regular Papers, 2019Co-Authors: Dawei Liu, Simon J Hollis, Bernard H StarkAbstract:Dual-output gate drivers for switched-mode Power supplies require low-side reference signals to be shifted to the switch-node potential. With the move to ultra-fast switching GaN converters, there is a commercial need to achieve switch-node slew-rates exceeding 100 V/ns, however, reported level shifters do not simultaneously achieve the required Power supply slew immunities and sub-ns propagation delays. This paper presents a novel design technique to achieve the first floating voltage level shifters that deliver slew-rate immunities above 100 V/ns and sub-ns delay in the same circuit. Step-by-step transistor-level design methods are presented. This technique is applied to improve a reported level shifter, and experimentally validated by fabricating this level shifter in a 180 nm high-voltage CMOS process. The final level shifter has zero static Power consumption, and is shown to have a sub-nanosecond delay across the whole operating range, a 200 V/ns positive Power-Rail slew tolerance, and infinite negative slew tolerance. The measured propagation delay decreases from 722 ps with the floating ground at −1.5 V, to 532 ps for a floating ground of 45 V, and the Power consumption is 30.3 pJ per transition at 45 V. It has a figure of merit of 0.06 ns/( $\mu $ mV), which is an $1.7\times $ improvement on the next best reported level shifter for this type of application.
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design of 370 ps delay floating voltage level shifters with 30 v ns Power supply slew tolerance
IEEE Transactions on Circuits and Systems Ii-express Briefs, 2016Co-Authors: Dawei Liu, Simon J Hollis, Harry C P Dymond, Neville Mcneill, Bernard H StarkAbstract:A new design method for producing high-performance and Power-Rail slew-tolerant floating-voltage level shifters is presented, offering increased speed, reduced Power consumption, and smaller layout area compared with previous designs. The method uses an energy-saving pulse-triggered input, a high-bandwidth current mirror, and a simple full latch composed of two inverters. A number of optimizations are explored in detail, resulting in a presented design with a $dV_{dd}/{dt}$ slew immunity of 30 V/ns, and near-zero static Power dissipation in a 180-nm technology. Experimental results show a delay of below 370 ps for a level-shift range of 8–20 V. Postlayout simulation puts the energy consumption at 2.6 pJ/bit at 4 V and 7.2 pJ/bit at 20 V, with near symmetric rise and fall delays.