The Experts below are selected from a list of 3633 Experts worldwide ranked by ideXlab platform
Masashi Shimanouchi - One of the best experts on this subject based on the ideXlab platform.
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theory model and applications of non gaussian probability density functions for Random Jitter noise with non white power spectral densities
International Test Conference, 2013Co-Authors: Daniel Chow, Masashi ShimanouchiAbstract:In high speed data communications, timing Jitter and voltage noise analyses often depend on mathematical models to predict long-term reliability of the system, typically merited by a low bit error ratio (BER). Many methods involve the extrapolation of Random Jitter (RJ) and Random noise (RN) to very low BER, assuming that RJ is white Gaussian noise. In reality, RJ spectra are not always white. Thus, RJ statistical distributions can deviate from an ideal Gaussian, affecting the accuracy of extrapolations. This paper presents a theory and model for relating RJ distributions with colored spectra. We apply this model to various filtered RJ spectra, including the extreme case of Brownian (1/f2) noise, and show correlation between simulation and measurement.
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ITC - Theory, model, and applications of non-Gaussian probability density functions for Random Jitter/noise with non-white power spectral densities
2013 IEEE International Test Conference (ITC), 2013Co-Authors: Daniel Chow, Masashi ShimanouchiAbstract:In high speed data communications, timing Jitter and voltage noise analyses often depend on mathematical models to predict long-term reliability of the system, typically merited by a low bit error ratio (BER). Many methods involve the extrapolation of Random Jitter (RJ) and Random noise (RN) to very low BER, assuming that RJ is white Gaussian noise. In reality, RJ spectra are not always white. Thus, RJ statistical distributions can deviate from an ideal Gaussian, affecting the accuracy of extrapolations. This paper presents a theory and model for relating RJ distributions with colored spectra. We apply this model to various filtered RJ spectra, including the extreme case of Brownian (1/f2) noise, and show correlation between simulation and measurement.
Michael M. Green - One of the best experts on this subject based on the ideXlab platform.
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Design of CML Ring Oscillators With Low Supply Sensitivity
IEEE Transactions on Circuits and Systems I: Regular Papers, 2013Co-Authors: Xiaoyan Gui, Michael M. GreenAbstract:The causes of supply noise-induced frequency variation in CML ring oscillators are investigated and a novel circuit topology that reduces the supply sensitivity is presented. It is shown that this technique causes only a slight reduction in the maximum oscillation frequency and maintains nearly the same Random Jitter generation while greatly reducing the sinusoidal Jitter caused by power supply variation. Measurement results from a prototype chip fabricated in 0.18 μm CMOS process verify the effectiveness of the proposed technique.
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CICC - High-speed CMOS ring oscillators with low supply sensitivity
IEEE Custom Integrated Circuits Conference 2010, 2010Co-Authors: Xiaoyan Gui, Michael M. GreenAbstract:A novel circuit topology for CMOS CML ring oscillators that reduces the supply sensitivity is presented. It is shown that this technique causes only a slight reduction in the maximum frequency of the oscillator and maintains the same Random Jitter generation while greatly reducing the sinusoidal Jitter caused by power supply variation. Measurement results from a prototype chip fabricated in 0.18µm CMOS process verify the effectiveness of the proposed technique.
Jiunlang Huang - One of the best experts on this subject based on the ideXlab platform.
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On-Chip Random Jitter Testing Using Low Tap-Count Coarse Delay Lines
Journal of Electronic Testing, 2006Co-Authors: Jiunlang HuangAbstract:An on-chip RMS Jitter testing technique for design-for-test (DfT) applications is presented in this paper. In addition to utilizing a less complicated low tap-count variable delay line to sample the Jitter’s cumulative density function (CDF), a sophisticated post-processing algorithm is developed to enhance process variation tolerance. Our simulation results show that using an eight-tap delay line, the probability of making correct pass/fail decisions is higher than 99% in the presence of up to 30% delay line value deviations.
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A Random Jitter Extraction Technique in the Presence of Sinusoidal Jitter
2006Co-Authors: Jiunlang HuangAbstract:In this paper, a Random Jitter (RJ) extraction technique in the presence of sinusoidal Jitter (SJ) is proposed for on-chip Jitter tolerance testing applications. First, the period-tracking technique (Kuo and Huang, 2006) is utilized to derive the SJ frequency and amplitude information. Then, using the same design-for-test (DfT) circuitry, samples from the total Jitter cumulative distribution function (CDF) are taken. From the SJ information and CDF samples, a binary search method is utilized to obtain the RJ sigma value. The features of the proposed technique include low delay line resolution requirement and high process variation tolerance. Simulation results are performed and shown to validate the proposed technique
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Random Jitter testing using low tap count delay lines
Asian Test Symposium, 2005Co-Authors: Jiunlang HuangAbstract:In this paper, a low-cost and process-insensitive Random Jitter testing algorithm is proposed for on-chip design-for-test applications. The algorithm incurs low hardware cost as it utilizes a low tap-count delay line to extract the RMS Jitter information. Furthermore, the proposed algorithm can tolerate reasonable delay line deviations. Our simulation results show that using an eight-tap delay line, the probability of making correct pass/fail decisions is higher than 99% in the presence of up to 30% delay line deviations
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Asian Test Symposium - Random Jitter Testing Using Low Tap-Count Delay Lines
14th Asian Test Symposium (ATS'05), 2005Co-Authors: Jiunlang HuangAbstract:In this paper, a low-cost and process-insensitive Random Jitter testing algorithm is proposed for on-chip design-for-test applications. The algorithm incurs low hardware cost as it utilizes a low tap-count delay line to extract the RMS Jitter information. Furthermore, the proposed algorithm can tolerate reasonable delay line deviations. Our simulation results show that using an eight-tap delay line, the probability of making correct pass/fail decisions is higher than 99% in the presence of up to 30% delay line deviations
Jacob A Abraham - One of the best experts on this subject based on the ideXlab platform.
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indirect method for Random Jitter measurement on socs using critical path characterization
European Test Symposium, 2012Co-Authors: Jaewook Lee, Ji Hwan Chun, Jacob A AbrahamAbstract:This paper presents a new method for Random Jitter measurement on systems-on-a-chip (SoCs) by exploiting shmoo plotting in automatic test equipment (ATE). After finding the maximum operating frequency of a microprocessor using functional test patterns that can sensitize its critical paths, the proposed method constructs a cumulative distribution function (CDF) whose standard deviation represents the root mean square (RMS) value of the Random Jitter of the clock signals used in the microprocessor. By leveraging tester period resolution with a frequency multiplying phase-locked loop (PLL) in the SoC, the shmoo plot with a fine period step size can detect the Jitter component in the clock signal, which reflects the actual Jitter that most critical paths undergo. The proposed idea was verified with circuit-level simulations, and was validated by silicon measurements using one of the latest SoC products.
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European Test Symposium - Indirect method for Random Jitter measurement on SoCs using critical path characterization
2012 17th IEEE European Test Symposium (ETS), 2012Co-Authors: Jaewook Lee, Ji Hwan Chun, Jacob A AbrahamAbstract:This paper presents a new method for Random Jitter measurement on systems-on-a-chip (SoCs) by exploiting shmoo plotting in automatic test equipment (ATE). After finding the maximum operating frequency of a microprocessor using functional test patterns that can sensitize its critical paths, the proposed method constructs a cumulative distribution function (CDF) whose standard deviation represents the root mean square (RMS) value of the Random Jitter of the clock signals used in the microprocessor. By leveraging tester period resolution with a frequency multiplying phase-locked loop (PLL) in the SoC, the shmoo plot with a fine period step size can detect the Jitter component in the clock signal, which reflects the actual Jitter that most critical paths undergo. The proposed idea was verified with circuit-level simulations, and was validated by silicon measurements using one of the latest SoC products.
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a novel characterization technique for high speed i o mixed signal circuit components using Random Jitter injection
Asia and South Pacific Design Automation Conference, 2010Co-Authors: Ji Hwan Chun, Jaewook Lee, Jacob A AbrahamAbstract:Timing problems in high-speed serial communications are mitigated with phase-interpolator (PI) circuitry. Linearity testing of PI has been challenging, even though PI is widely used in modern high speed I/O architectures. Previous research has focused on implementing additional built-in circuits to measure PI linearity. In this paper, we present a cost effective PI linearity measurement technique which requires no significant modification of existing I/O circuits. Our method uses Jitter distributions obtained from Random Jitter injected into the data channel. Two distributions are separately obtained using undersampling and sampling using PI. The proposed algorithm calculates the differential nonlinearity (DNL) from the difference of these distributions. Simulation results show that the average prediction RMS error for the DNL calculation is 0.31 LSB.
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ASP-DAC - A novel characterization technique for high speed I/O mixed signal circuit components using Random Jitter injection
2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 2010Co-Authors: Ji Hwan Chun, Jaewook Lee, Jacob A AbrahamAbstract:Timing problems in high-speed serial communications are mitigated with phase-interpolator (PI) circuitry. Linearity testing of PI has been challenging, even though PI is widely used in modern high speed I/O architectures. Previous research has focused on implementing additional built-in circuits to measure PI linearity. In this paper, we present a cost effective PI linearity measurement technique which requires no significant modification of existing I/O circuits. Our method uses Jitter distributions obtained from Random Jitter injected into the data channel. Two distributions are separately obtained using undersampling and sampling using PI. The proposed algorithm calculates the differential nonlinearity (DNL) from the difference of these distributions. Simulation results show that the average prediction RMS error for the DNL calculation is 0.31 LSB.
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A Random Jitter RMS Estimation Technique for BIST Applications
2009 Asian Test Symposium, 2009Co-Authors: Ji Hwan Chun, Jacob A AbrahamAbstract:This paper describes a RMS value measurement technique for Random Jitter. A Jittery clock signal is combined with a reference clock signal using an OR operation and an AND operation in sequence, and the pulse width outputs modulated by the amount of the Random Jitter are used to charge or discharge a capacitor. The voltage at the capacitor, in turn, modulates the frequency of VCO having a current-starved inverter, and whose frequency difference from the OR operation and the AND operation is used in calculating the RMS value of the Random Jitter. Circuit-level simulations show the validity of the proposed technique for up to 20% peak-to-peak Jitter in the clock even with process variations. The proposed technique can be applied to BIST solutions for Random Jitter measurement on a transmitted clock signal.
Daniel Chow - One of the best experts on this subject based on the ideXlab platform.
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theory model and applications of non gaussian probability density functions for Random Jitter noise with non white power spectral densities
International Test Conference, 2013Co-Authors: Daniel Chow, Masashi ShimanouchiAbstract:In high speed data communications, timing Jitter and voltage noise analyses often depend on mathematical models to predict long-term reliability of the system, typically merited by a low bit error ratio (BER). Many methods involve the extrapolation of Random Jitter (RJ) and Random noise (RN) to very low BER, assuming that RJ is white Gaussian noise. In reality, RJ spectra are not always white. Thus, RJ statistical distributions can deviate from an ideal Gaussian, affecting the accuracy of extrapolations. This paper presents a theory and model for relating RJ distributions with colored spectra. We apply this model to various filtered RJ spectra, including the extreme case of Brownian (1/f2) noise, and show correlation between simulation and measurement.
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ITC - Theory, model, and applications of non-Gaussian probability density functions for Random Jitter/noise with non-white power spectral densities
2013 IEEE International Test Conference (ITC), 2013Co-Authors: Daniel Chow, Masashi ShimanouchiAbstract:In high speed data communications, timing Jitter and voltage noise analyses often depend on mathematical models to predict long-term reliability of the system, typically merited by a low bit error ratio (BER). Many methods involve the extrapolation of Random Jitter (RJ) and Random noise (RN) to very low BER, assuming that RJ is white Gaussian noise. In reality, RJ spectra are not always white. Thus, RJ statistical distributions can deviate from an ideal Gaussian, affecting the accuracy of extrapolations. This paper presents a theory and model for relating RJ distributions with colored spectra. We apply this model to various filtered RJ spectra, including the extreme case of Brownian (1/f2) noise, and show correlation between simulation and measurement.
