The Experts below are selected from a list of 16086 Experts worldwide ranked by ideXlab platform
Tiensheng Chao - One of the best experts on this subject based on the ideXlab platform.
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Novel 2-Bit/Cell Wrapped-Select-Gate SONOS TFT Memory Using Source-Side Injection for NOR-Type Flash Array
IEEE Electron Device Letters, 2012Co-Authors: Kuan-ti Wang, Fang-chang Hsueh, Tsung-yu Chiang, Chia-chun Liao, Li-chen Yen, Tiensheng ChaoAbstract:This letter is the first to successfully demonstrate the 2-Bit/Cell wrapped-selected-gate (WSG) SONOS thin-film transistor (TFT) memory using source-side injection (SSI). Because of the higher programming efficiency of SSI, a memory window of approximately 3 V can be easily achieved in 10 μs and 30 ms for the program and erase modes, respectively. In addition, we performed an exCellent 2-Bit/Cell distinguish margin for 3-V memory window in WSG-SONOS TFT memory. The optimal reliability of the endurance and data retention tests can be executed by adjusting the applied voltage appropriately.
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highly reliable multilevel and 2 Bit Cell operation of wrapped select gate wsg sonos memory
IEEE Electron Device Letters, 2007Co-Authors: Woeicherng Wu, Tiensheng Chao, Wuchin Peng, Wenluh Yang, Jerchyi Wang, Jianhao Chen, Tsungyu Yang, Tsungmin Hsieh, Jhyy Cheng LiouAbstract:In this letter, high-performance and reliable wrapped select gate (WSG) polysilicon-oxide-nitride-oxide-silicon (SONOS) memory Cells with multilevel and 2-Bit/Cell operation have been successfully demonstrated. The multilevel storage is easily obtained with fast program/erase speed (10 mus/5 ms) and low programming current (3.5 muA) for our WSG SONOS by a source-side injection. Besides the exCellent reliability properties of our multilevel WSG-SONOS memory including unconsidered gate and drain disturbance, long charge retention (>150degC) and good endurance (>104) are also presented. This novel WSG-SONOS memory with a multilevel and 2-Bit/Cell operation can be used in future high-density and high-performance memory application
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Highly Reliable Multilevel and 2-Bit/Cell Operation of Wrapped Select Gate (WSG) SONOS Memory
IEEE Electron Device Letters, 2007Co-Authors: Tiensheng Chao, Wuchin Peng, Wenluh Yang, Jerchyi Wang, Jianhao Chen, Tsungyu Yang, Chao-sung Lai, Chien-hsing Lee, Tsungmin HsiehAbstract:In this letter, high-performance and reliable wrapped select gate (WSG) polysilicon-oxide-nitride-oxide-silicon (SONOS) memory Cells with multilevel and 2-Bit/Cell operation have been successfully demonstrated. The multilevel storage is easily obtained with fast program/erase speed (10 mus/5 ms) and low programming current (3.5 muA) for our WSG SONOS by a source-side injection. Besides the exCellent reliability properties of our multilevel WSG-SONOS memory including unconsidered gate and drain disturbance, long charge retention (>150degC) and good endurance (>104) are also presented. This novel WSG-SONOS memory with a multilevel and 2-Bit/Cell operation can be used in future high-density and high-performance memory application
David Blaauw - One of the best experts on this subject based on the ideXlab platform.
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a 28 nm configurable memory tcam bcam sram using push rule 6t Bit Cell enabling logic in memory
IEEE Journal of Solid-state Circuits, 2016Co-Authors: Supreet Jeloka, Naveen Bharathwaj Akesh, Dennis Sylvester, David BlaauwAbstract:Conventional content addressable memory (BCAM and TCAM) uses specialized 10T/16T Bit Cells that are significantly larger than 6T SRAM Cells. A new BCAM/TCAM is proposed that can operate with standard push-rule 6T SRAM Cells, reducing array area by 2–5× and allowing reconfiguration of the SRAM as a CAM. In this way, chip area and overall capacitance can be reduced, leading to higher energy efficiency for search operations. In addition, the configurable memory can perform Bit-wise logical operations: “AND” and “NOR” on two or more words stored within the array. Thus, the configurable memory with CAM and logical function capability can be used to off-load specific computational operations to the memory, improving system performance and efficiency. Using a 6T 28 nm FDSOI SRAM Bit Cell, the 64×64 (4 kb) BCAM achieves 370 MHz at 1 V and consumes 0.6 fJ/search/Bit. A logical operation between two 64 Bit words achieves 787 MHz at 1 V.
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A 28 nm Configurable Memory (TCAM/BCAM/SRAM) Using Push-Rule 6T Bit Cell Enabling Logic-in-Memory
IEEE Journal of Solid-State Circuits, 2016Co-Authors: Supreet Jeloka, Naveen Bharathwaj Akesh, Dennis Sylvester, David BlaauwAbstract:Conventional content addressable memory (BCAM and TCAM) uses specialized 10T/16T Bit Cells that are significantly larger than 6T SRAM Cells. A new BCAM/TCAM is proposed that can operate with standard push-rule 6T SRAM Cells, reducing array area by 2-5× and allowing reconfiguration of the SRAM as a CAM. In this way, chip area and overall capacitance can be reduced, leading to higher energy efficiency for search operations. In addition, the configurable memory can perform Bit-wise logical operations: “AND” and “NOR” on two or more words stored within the array. Thus, the configurable memory with CAM and logical function capability can be used to off-load specific computational operations to the memory, improving system performance and efficiency. Using a 6T 28 nm FDSOI SRAM Bit Cell, the 64×64 (4 kb) BCAM achieves 370 MHz at 1 V and consumes 0.6 fJ/search/Bit. A logical operation between two 64 Bit words achieves 787 MHz at 1 V.
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a configurable tcam bcam sram using 28nm push rule 6t Bit Cell
Symposium on VLSI Circuits, 2015Co-Authors: Supreet Jeloka, Naveen Bharathwaj Akesh, Dennis Sylvester, David BlaauwAbstract:Conventional Content Addressable Memory (BCAM and TCAM) uses specialized 10T / 16T Bit Cells that are significantly larger than 6T SRAM Cells. We propose a new BCAM/TCAM that can operate with standard push-rule 6T SRAM Cells, reducing array area by 2–5× and allowing reconfiguration of the CAM as an SRAM. Using a 6T 28nm FDSOI SRAM Bit Cell, the 64×64 (4kb) BCAM achieves 370 MHz at 1V and consumes 0.6fJ/search/Bit.
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VLSIC - A configurable TCAM/BCAM/SRAM using 28nm push-rule 6T Bit Cell
2015 Symposium on VLSI Circuits (VLSI Circuits), 2015Co-Authors: Supreet Jeloka, Naveen Bharathwaj Akesh, Dennis Sylvester, David BlaauwAbstract:Conventional Content Addressable Memory (BCAM and TCAM) uses specialized 10T / 16T Bit Cells that are significantly larger than 6T SRAM Cells. We propose a new BCAM/TCAM that can operate with standard push-rule 6T SRAM Cells, reducing array area by 2–5× and allowing reconfiguration of the CAM as an SRAM. Using a 6T 28nm FDSOI SRAM Bit Cell, the 64×64 (4kb) BCAM achieves 370 MHz at 1V and consumes 0.6fJ/search/Bit.
Tsungmin Hsieh - One of the best experts on this subject based on the ideXlab platform.
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highly reliable multilevel and 2 Bit Cell operation of wrapped select gate wsg sonos memory
IEEE Electron Device Letters, 2007Co-Authors: Woeicherng Wu, Tiensheng Chao, Wuchin Peng, Wenluh Yang, Jerchyi Wang, Jianhao Chen, Tsungyu Yang, Tsungmin Hsieh, Jhyy Cheng LiouAbstract:In this letter, high-performance and reliable wrapped select gate (WSG) polysilicon-oxide-nitride-oxide-silicon (SONOS) memory Cells with multilevel and 2-Bit/Cell operation have been successfully demonstrated. The multilevel storage is easily obtained with fast program/erase speed (10 mus/5 ms) and low programming current (3.5 muA) for our WSG SONOS by a source-side injection. Besides the exCellent reliability properties of our multilevel WSG-SONOS memory including unconsidered gate and drain disturbance, long charge retention (>150degC) and good endurance (>104) are also presented. This novel WSG-SONOS memory with a multilevel and 2-Bit/Cell operation can be used in future high-density and high-performance memory application
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Highly Reliable Multilevel and 2-Bit/Cell Operation of Wrapped Select Gate (WSG) SONOS Memory
IEEE Electron Device Letters, 2007Co-Authors: Tiensheng Chao, Wuchin Peng, Wenluh Yang, Jerchyi Wang, Jianhao Chen, Tsungyu Yang, Chao-sung Lai, Chien-hsing Lee, Tsungmin HsiehAbstract:In this letter, high-performance and reliable wrapped select gate (WSG) polysilicon-oxide-nitride-oxide-silicon (SONOS) memory Cells with multilevel and 2-Bit/Cell operation have been successfully demonstrated. The multilevel storage is easily obtained with fast program/erase speed (10 mus/5 ms) and low programming current (3.5 muA) for our WSG SONOS by a source-side injection. Besides the exCellent reliability properties of our multilevel WSG-SONOS memory including unconsidered gate and drain disturbance, long charge retention (>150degC) and good endurance (>104) are also presented. This novel WSG-SONOS memory with a multilevel and 2-Bit/Cell operation can be used in future high-density and high-performance memory application
Kaushik Roy - One of the best experts on this subject based on the ideXlab platform.
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High-Density SOT-MRAM Based on Shared Bitline Structure
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2018Co-Authors: Yeongkyo Seo, Kaushik RoyAbstract:This brief proposes a new design technique for spin-orBit torque magnetic random access memory (SOT-MRAM), suitable for high-density and low-power on-chip cache applications. A Bitline of the proposed memory Bit Cell is shared with that of an adjacent Bit Cell leading to a reduction in the number of metals along the column direction. This results in higher integration density due to improved metal pitch limited region. The proposed memory can optimize the Bit-Cell area by aggressively reducing the size of write access transistor, since SOT-based switching operation of SOT devices translates to smaller size of write access transistor. Furthermore, the proposed SOT-MRAM still retains the advantages of SOT-MRAM such as low write energy dissipation, high read-disturb margin, and improved reliability of magnetic tunnel junction. In comparison with the conventional SOT-MRAM Bit Cells, our proposed MRAM Bit Cell can have 20% less Bit-Cell area. Even compared with the standard STT-MRAM, our proposed Bit Cell still achieves higher integration density. Moreover, the shared Bitline SOT-MRAM achieves $> 6\times $ lower write power and higher read-disturb margin than does the STT-MRAM.
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modeling and design space exploration for Bit Cells based on voltage assisted switching of magnetic tunnel junctions
IEEE Transactions on Electron Devices, 2016Co-Authors: Saima Sharmin, Akhilesh Jaiswal, Kaushik RoyAbstract:The effect of voltage on the anisotropy of a magnetic tunnel junction (MTJ) is of substantial interest for low-power nonvolatile memory applications. In this paper, we develop a device-to-Bit-Cell level simulation framework for voltage-assisted switching of the MTJs, which can satisfactorily reproduce the published experimental data. Our simulation framework is based on a coupled Landau–Lifshitz–Gilbert–Slonczewski equation and nonequilibrium greens function formalism. Using this simulation framework, we investigate the effect of scaling the oxide thickness of an MTJ to enhance the electric field effect. Although it seems attractive for an isolated device, yet, in a Bit-Cell configuration, reducing the oxide thickness leads to an increase in the supply voltage. In addition, we demonstrate that the unipolar characteristic of the voltage-assisted switching leads to write failures depending on the initial state stored in the MTJ. We, therefore, suggest a read before write scheme exhiBiting approximately $2\times $ improvement in the write energy consumption at a Bit-Cell level compared with a standard STT-MRAM for iso-oxide thickness. However, the latency overhead associated with voltage-assisted MTJs results in a $1.55\times $ degradation of the write speed. Moreover, our layout analysis indicates that the Bit-Cell area reduction is constrained by the metal pitch, in spite of smaller access transistors.
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Failure Mitigation Techniques for 1T-1MTJ Spin-Transfer Torque MRAM Bit-Cells
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2014Co-Authors: Xuanyao Fong, Sri Harsha Choday, Yusung Kim, Kaushik RoyAbstract:The emergence of spin-transfer torque magnetic RAM (STT-MRAM) as a leading candidate for future high-performance nonvolatile memory has led to increased research interest. Current STT-MRAM technology faces several major obstacles in attaining its potential. One of the major issues is in the design of 1T-1MTJ STT-MRAM Bit-Cells under process variations: the Bit-Cells need to be significantly upsized to improve Bit-Cell failure, resulting in increased Bit-Cell area and power dissipation. In this paper, we analyze four circuit-level solutions that enable smaller 1T-1MTJ STT-MRAM Bit-Cells with improved yield, namely, Bit-line voltage boosting, word-line voltage boosting, access transistor body biasing, and an applied external magnetic field. Results from simulation using 45-nm bulk CMOS access transistor and 40-nm magnetic tunneling junction technology show that word-line voltage boosting can be the best failure mitigation technique. Bit-Cells designed with word-line boosting for write has a Bit-Cell area reduced by > 75% at iso-failure probability, compared to Bit-Cells without any failure mitigation technique. When Bit-Cell failure probability is optimized instead, 5 Oe of applied external magnetic field assisted write reduces power consumption by 15% , compared to Bit-Cells designed without failure mitigation techniques.
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Bit-Cell Level Optimization for Non-volatile Memories Using Magnetic Tunnel Junctions and Spin-Transfer Torque Switching
IEEE Transactions on Nanotechnology, 2012Co-Authors: Xuanyao Fong, Sri Harsha Choday, Kaushik RoyAbstract:Spin-transfer torque magnetic random access memories (STT-MRAM), using magnetic tunnel junctions (MTJ), is a resistive memory technology that has spurred significant research interest due to its potential for on-chip, high-density, high-speed, low-power, and non-volatile memory. However, due to conflicting read and write requirements, there is a need to develop optimization techniques for designing STT-MRAM Bit-Cells to minimize read and write failures. We propose an optimization technique that minimizes read and write failures by proper selection of Bit-Cell configuration and by proper access transistor sizing. A mixed-mode simulation framework was developed to evaluate the effectiveness of our optimization technique. Our simulation framework captures the transport physics in the MTJ using Non-Equilibrium Green's Function method and self-consistently solves the MTJ magnetization dynamics using Landau-Lifshitz-Gilbert equation augmented with the full Slonczewski spin-torque term. The electrical parameters of the MTJ are then encapsulated in a Verilog-A model and used in HSPICE to perform Bit-Cell level optimization. The optimization technique is applied to STT-MRAM Bit-Cells designed using 45 nm bulk and 45 nm silicon-on-insulator CMOS technologies. Finally, predictions are made for optimized STT-MRAM Bit-Cells designed in 16 nm predictive technology.
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KNACK: A hybrid spin-charge mixed-mode simulator for evaluating different genres of spin-transfer torque MRAM Bit-Cells
2011 International Conference on Simulation of Semiconductor Processes and Devices, 2011Co-Authors: Xuanyao Fong, Sri Harsha Choday, Sumeet Kumar Gupta, Niladri Narayan Mojumder, Charles Augustine, Kaushik RoyAbstract:The storage device in spin-transfer torque MRAM (STT-MRAM) is the magnetic tunneling junction (MTJ) and several models for the MTJ have been proposed. However, a simulation framework that captures device physics at the atomistic level when simulating STT-MRAM at the Bit-Cell level is lacking. We propose a simulation framework (KNACK) which models the MTJ at the atomistic level using the Non-Equilibrium Green's Function (NEGF) formalism and uses the NEGF model in conjunction with our STT-MRAM Bit-Cell circuit model for circuit-level simulations. Our simulation framework accepts I–V and C-V characteristics of the access device input either as lookup tables or as compact models. We show that with appropriate device and Bit-Cell parameters, our simulation framework has the ability to capture MTJ physics and simulate different genres of STT-MRAM Bit-Cells with results in agreement with experiments.
Supreet Jeloka - One of the best experts on this subject based on the ideXlab platform.
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a 28 nm configurable memory tcam bcam sram using push rule 6t Bit Cell enabling logic in memory
IEEE Journal of Solid-state Circuits, 2016Co-Authors: Supreet Jeloka, Naveen Bharathwaj Akesh, Dennis Sylvester, David BlaauwAbstract:Conventional content addressable memory (BCAM and TCAM) uses specialized 10T/16T Bit Cells that are significantly larger than 6T SRAM Cells. A new BCAM/TCAM is proposed that can operate with standard push-rule 6T SRAM Cells, reducing array area by 2–5× and allowing reconfiguration of the SRAM as a CAM. In this way, chip area and overall capacitance can be reduced, leading to higher energy efficiency for search operations. In addition, the configurable memory can perform Bit-wise logical operations: “AND” and “NOR” on two or more words stored within the array. Thus, the configurable memory with CAM and logical function capability can be used to off-load specific computational operations to the memory, improving system performance and efficiency. Using a 6T 28 nm FDSOI SRAM Bit Cell, the 64×64 (4 kb) BCAM achieves 370 MHz at 1 V and consumes 0.6 fJ/search/Bit. A logical operation between two 64 Bit words achieves 787 MHz at 1 V.
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A 28 nm Configurable Memory (TCAM/BCAM/SRAM) Using Push-Rule 6T Bit Cell Enabling Logic-in-Memory
IEEE Journal of Solid-State Circuits, 2016Co-Authors: Supreet Jeloka, Naveen Bharathwaj Akesh, Dennis Sylvester, David BlaauwAbstract:Conventional content addressable memory (BCAM and TCAM) uses specialized 10T/16T Bit Cells that are significantly larger than 6T SRAM Cells. A new BCAM/TCAM is proposed that can operate with standard push-rule 6T SRAM Cells, reducing array area by 2-5× and allowing reconfiguration of the SRAM as a CAM. In this way, chip area and overall capacitance can be reduced, leading to higher energy efficiency for search operations. In addition, the configurable memory can perform Bit-wise logical operations: “AND” and “NOR” on two or more words stored within the array. Thus, the configurable memory with CAM and logical function capability can be used to off-load specific computational operations to the memory, improving system performance and efficiency. Using a 6T 28 nm FDSOI SRAM Bit Cell, the 64×64 (4 kb) BCAM achieves 370 MHz at 1 V and consumes 0.6 fJ/search/Bit. A logical operation between two 64 Bit words achieves 787 MHz at 1 V.
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a configurable tcam bcam sram using 28nm push rule 6t Bit Cell
Symposium on VLSI Circuits, 2015Co-Authors: Supreet Jeloka, Naveen Bharathwaj Akesh, Dennis Sylvester, David BlaauwAbstract:Conventional Content Addressable Memory (BCAM and TCAM) uses specialized 10T / 16T Bit Cells that are significantly larger than 6T SRAM Cells. We propose a new BCAM/TCAM that can operate with standard push-rule 6T SRAM Cells, reducing array area by 2–5× and allowing reconfiguration of the CAM as an SRAM. Using a 6T 28nm FDSOI SRAM Bit Cell, the 64×64 (4kb) BCAM achieves 370 MHz at 1V and consumes 0.6fJ/search/Bit.
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VLSIC - A configurable TCAM/BCAM/SRAM using 28nm push-rule 6T Bit Cell
2015 Symposium on VLSI Circuits (VLSI Circuits), 2015Co-Authors: Supreet Jeloka, Naveen Bharathwaj Akesh, Dennis Sylvester, David BlaauwAbstract:Conventional Content Addressable Memory (BCAM and TCAM) uses specialized 10T / 16T Bit Cells that are significantly larger than 6T SRAM Cells. We propose a new BCAM/TCAM that can operate with standard push-rule 6T SRAM Cells, reducing array area by 2–5× and allowing reconfiguration of the CAM as an SRAM. Using a 6T 28nm FDSOI SRAM Bit Cell, the 64×64 (4kb) BCAM achieves 370 MHz at 1V and consumes 0.6fJ/search/Bit.