Buffer Amplifier - Explore the Science & Experts | ideXlab

Scan Science and Technology

Contact Leading Edge Experts & Companies

Buffer Amplifier

The Experts below are selected from a list of 2862 Experts worldwide ranked by ideXlab platform

Chih-wen Lu – 1st expert on this subject based on the ideXlab platform

  • A RAIL-TO-RAIL Buffer Amplifier FOR LCD DRIVER
    Journal of Circuits Systems and Computers, 2020
    Co-Authors: Chih-wen Lu, Ching-min Hsiao

    Abstract:

    A high-speed low-power rail-to-rail Buffer Amplifier, which is suitable for liquid crystal display driver applications, is proposed. An offset voltage is intentionally built in the second stage to cut off the transistors of last stage from the output node in the stable state and hence achieve low dc power consumption. The input referred offset voltage due to the built-in offset is very small. The Buffer draws little current while static but has a large driving capability while transient. An experimental prototype Buffer Amplifier implemented in a 0.35-μm CMOS technology demonstrates that the circuit can operate under a wide power supply range. Quiescent current of 5 μA is measured. The Buffer exhibits the settling time of 1.5 μs for a voltage swing of 0.1 ~ (VDD – 0.1) V under a 600 pF capacitance load. The area of this Buffer is 30 × 98 μm2. The measured data show that the proposed output Buffer Amplifier is very suitable for LCD driver applications.

  • A low-quiescent current two-input/output Buffer Amplifier for LCDs
    2012 IEEE International Symposium on Circuits and Systems (ISCAS), 2012
    Co-Authors: Chih-wen Lu, Salvatore Pennisi

    Abstract:

    This study proposes a low-quiescent current two-input/output Buffer Amplifier for LCD applications. A current reuse technique is employed in the output stage of the Buffer Amplifier to reduce the quiescent current consumption. An experimental prototype 6-bit LCD column driver with the proposed Buffer Amplifiers implemented in a 0.35-μm CMOS technology demonstrates that an average value of 0.6 μA static current is consumed in one channel driver. The settling time to settle within 0.2% of the final voltage is 6 μs under a 30-KΩ-resistance and 30-pF-capacitance load. The area of this two-input/output Buffer Amplifier is 21.5 μm × 190 μm.

  • a low quiescent current two input output Buffer Amplifier for lcds
    International Symposium on Circuits and Systems, 2012
    Co-Authors: Chih-wen Lu, Salvatore Pennisi

    Abstract:

    This study proposes a low-quiescent current two-input/output Buffer Amplifier for LCD applications. A current reuse technique is employed in the output stage of the Buffer Amplifier to reduce the quiescent current consumption. An experimental prototype 6-bit LCD column driver with the proposed Buffer Amplifiers implemented in a 0.35-µm CMOS technology demonstrates that an average value of 0.6 µA static current is consumed in one channel driver. The settling time to settle within 0.2% of the final voltage is 6 µs under a 30-KΩ-resistance and 30-pF-capacitance load. The area of this two-input/output Buffer Amplifier is 21.5 µm × 190 µm.

Salvatore Pennisi – 2nd expert on this subject based on the ideXlab platform

  • Dual Push–Pull High-Speed Rail-to-Rail CMOS Buffer Amplifier for Flat-Panel Displays
    IEEE Transactions on Circuits and Systems Ii-express Briefs, 2018
    Co-Authors: A. D. Grasso, G. Palumbo, Salvatore Pennisi

    Abstract:

    This brief presents the experimental validation of a low-power, large output swing, class-AB Buffer Amplifier for column drivers of active-matrix flat-panel displays. By exploiting two complementary input Amplifiers and a dual-path push–pull output stage, the proposed circuit achieves high-drive performance and rail-to-rail operation. In addition, two current boosters allow area optimization of the output diving transistors by dynamically lowering their threshold voltage. Implemented in a standard triple-well CMOS 0.35- ${\mu }{\text{m}}$ technology and supplied from a 3-V supply, the proposed Buffer Amplifier can drive a 1-nF column line load within a 1.11- ${\mu }\text{s}$ settling time under a full voltage swing, while drawing only 1.6 ${\mu }\text{A}$ quiescent current and occupying 5562 ${\mu }{\text{m}}^{{2}}$ of silicon area. As compared to the state of the art, the best figure of merit (pF/ ${\mu }\text{s}{\cdot } {\mu }\text{A}$ ) is found.

  • Self-Biased Dual-Path Push-Pull Output Buffer Amplifier for LCD Column Drivers
    IEEE Transactions on Circuits and Systems I: Regular Papers, 2014
    Co-Authors: A. D. Grasso, G. Palumbo, Davide Marano, Fermin Esparza-alfaro, Antonio J. Lopez-martin, Salvatore Pennisi

    Abstract:

    A high-performance Buffer Amplifier topology for liquid crystal display drivers is presented. The proposed Amplifier achieves fast driving performance and offers a rail-to-rail common-mode input range. Enhanced slewing and settling capabilities are achieved through a novel output stage performing dual-path push-pull operation. No additional biasing network is required to set the quiescent conditions of the class-AB output stage, since the output static current is inherently controlled by the input differential stage itself, without additional power dissipation. Experimental results demonstrate that the suggested Buffer can drive a 1000-pF capacitive load with a 5.7-V/μs slew-rate and a 0.71-μs settling time, while drawing 32-μA overall quiescent current from a 5-V power supply.

  • A low-quiescent current two-input/output Buffer Amplifier for LCDs
    2012 IEEE International Symposium on Circuits and Systems (ISCAS), 2012
    Co-Authors: Chih-wen Lu, Salvatore Pennisi

    Abstract:

    This study proposes a low-quiescent current two-input/output Buffer Amplifier for LCD applications. A current reuse technique is employed in the output stage of the Buffer Amplifier to reduce the quiescent current consumption. An experimental prototype 6-bit LCD column driver with the proposed Buffer Amplifiers implemented in a 0.35-μm CMOS technology demonstrates that an average value of 0.6 μA static current is consumed in one channel driver. The settling time to settle within 0.2% of the final voltage is 6 μs under a 30-KΩ-resistance and 30-pF-capacitance load. The area of this two-input/output Buffer Amplifier is 21.5 μm × 190 μm.

G. Palumbo – 3rd expert on this subject based on the ideXlab platform

  • Dual Push–Pull High-Speed Rail-to-Rail CMOS Buffer Amplifier for Flat-Panel Displays
    IEEE Transactions on Circuits and Systems Ii-express Briefs, 2018
    Co-Authors: A. D. Grasso, G. Palumbo, Salvatore Pennisi

    Abstract:

    This brief presents the experimental validation of a low-power, large output swing, class-AB Buffer Amplifier for column drivers of active-matrix flat-panel displays. By exploiting two complementary input Amplifiers and a dual-path push–pull output stage, the proposed circuit achieves high-drive performance and rail-to-rail operation. In addition, two current boosters allow area optimization of the output diving transistors by dynamically lowering their threshold voltage. Implemented in a standard triple-well CMOS 0.35- ${\mu }{\text{m}}$ technology and supplied from a 3-V supply, the proposed Buffer Amplifier can drive a 1-nF column line load within a 1.11- ${\mu }\text{s}$ settling time under a full voltage swing, while drawing only 1.6 ${\mu }\text{A}$ quiescent current and occupying 5562 ${\mu }{\text{m}}^{{2}}$ of silicon area. As compared to the state of the art, the best figure of merit (pF/ ${\mu }\text{s}{\cdot } {\mu }\text{A}$ ) is found.

  • dual push pull high speed rail to rail cmos Buffer Amplifier for flat panel displays
    IEEE Transactions on Circuits and Systems Ii-express Briefs, 2018
    Co-Authors: A. D. Grasso, G. Palumbo, S. Pennisi

    Abstract:

    This brief presents the experimental validation of a low-power, large output swing, class-AB Buffer Amplifier for column drivers of active-matrix flat-panel displays. By exploiting two complementary input Amplifiers and a dual-path push–pull output stage, the proposed circuit achieves high-drive performance and rail-to-rail operation. In addition, two current boosters allow area optimization of the output diving transistors by dynamically lowering their threshold voltage. Implemented in a standard triple-well CMOS 0.35- ${\mu }{\text{m}}$ technology and supplied from a 3-V supply, the proposed Buffer Amplifier can drive a 1-nF column line load within a 1.11- ${\mu }\text{s}$ settling time under a full voltage swing, while drawing only 1.6 ${\mu }\text{A}$ quiescent current and occupying 5562 ${\mu }{\text{m}}^{{2}}$ of silicon area. As compared to the state of the art, the best figure of merit (pF/ ${\mu }\text{s}{\cdot } {\mu }\text{A}$ ) is found.

  • Dual Push–Pull High-Speed Rail-to-Rail CMOS Buffer Amplifier for Flat-Panel Displays
    IEEE Transactions on Circuits and Systems II: Express Briefs, 2018
    Co-Authors: A. D. Grasso, G. Palumbo, S. Pennisi

    Abstract:

    This brief presents the experimental validation of a low-power, large output swing, class-AB Buffer Amplifier for column drivers of active-matrix flat-panel displays. By exploiting two complementary input Amplifiers and a dual-path push- pull output stage, the proposed circuit achieves high-drive performance and rail-to-rail operation. In addition, two current boosters allow area optimization of the output diving transistors by dynamically lowering their threshold voltage. Implemented in a standard triple-well CMOS 0.35-μm technology and supplied from a 3-V supply, the proposed Buffer Amplifier can drive a 1-nF column line load within a 1.11-μs settling time under a full voltage swing, while drawing only 1.6 μA quiescent current and occupying 5562 μm2 of silicon area. As compared to the state of the art, the best figure of merit (pF/μs·μA) is found.