The Experts below are selected from a list of 2862 Experts worldwide ranked by ideXlab platform
Chih-wen Lu - One of the best experts on this subject based on the ideXlab platform.
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A RAIL-TO-RAIL Buffer Amplifier FOR LCD DRIVER
Journal of Circuits Systems and Computers, 2020Co-Authors: Chih-wen Lu, Ching-min HsiaoAbstract:A high-speed low-power rail-to-rail Buffer Amplifier, which is suitable for liquid crystal display driver applications, is proposed. An offset voltage is intentionally built in the second stage to cut off the transistors of last stage from the output node in the stable state and hence achieve low dc power consumption. The input referred offset voltage due to the built-in offset is very small. The Buffer draws little current while static but has a large driving capability while transient. An experimental prototype Buffer Amplifier implemented in a 0.35-μm CMOS technology demonstrates that the circuit can operate under a wide power supply range. Quiescent current of 5 μA is measured. The Buffer exhibits the settling time of 1.5 μs for a voltage swing of 0.1 ~ (VDD – 0.1) V under a 600 pF capacitance load. The area of this Buffer is 30 × 98 μm2. The measured data show that the proposed output Buffer Amplifier is very suitable for LCD driver applications.
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A low-quiescent current two-input/output Buffer Amplifier for LCDs
2012 IEEE International Symposium on Circuits and Systems (ISCAS), 2012Co-Authors: Chih-wen Lu, Salvatore PennisiAbstract:This study proposes a low-quiescent current two-input/output Buffer Amplifier for LCD applications. A current reuse technique is employed in the output stage of the Buffer Amplifier to reduce the quiescent current consumption. An experimental prototype 6-bit LCD column driver with the proposed Buffer Amplifiers implemented in a 0.35-μm CMOS technology demonstrates that an average value of 0.6 μA static current is consumed in one channel driver. The settling time to settle within 0.2% of the final voltage is 6 μs under a 30-KΩ-resistance and 30-pF-capacitance load. The area of this two-input/output Buffer Amplifier is 21.5 μm × 190 μm.
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a low quiescent current two input output Buffer Amplifier for lcds
International Symposium on Circuits and Systems, 2012Co-Authors: Chih-wen Lu, Salvatore PennisiAbstract:This study proposes a low-quiescent current two-input/output Buffer Amplifier for LCD applications. A current reuse technique is employed in the output stage of the Buffer Amplifier to reduce the quiescent current consumption. An experimental prototype 6-bit LCD column driver with the proposed Buffer Amplifiers implemented in a 0.35-µm CMOS technology demonstrates that an average value of 0.6 µA static current is consumed in one channel driver. The settling time to settle within 0.2% of the final voltage is 6 µs under a 30-KΩ-resistance and 30-pF-capacitance load. The area of this two-input/output Buffer Amplifier is 21.5 µm × 190 µm.
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ISCAS - A low-quiescent current two-input/output Buffer Amplifier for LCDs
2012 IEEE International Symposium on Circuits and Systems, 2012Co-Authors: Chih-wen Lu, Salvatore PennisiAbstract:This study proposes a low-quiescent current two-input/output Buffer Amplifier for LCD applications. A current reuse technique is employed in the output stage of the Buffer Amplifier to reduce the quiescent current consumption. An experimental prototype 6-bit LCD column driver with the proposed Buffer Amplifiers implemented in a 0.35-µm CMOS technology demonstrates that an average value of 0.6 µA static current is consumed in one channel driver. The settling time to settle within 0.2% of the final voltage is 6 µs under a 30-KΩ-resistance and 30-pF-capacitance load. The area of this two-input/output Buffer Amplifier is 21.5 µm × 190 µm.
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A COMPACT HIGH-SPEED LOW-POWER RAIL-TO-RAIL Buffer Amplifier FOR STEP-PULSE SIGNALS
Journal of Circuits Systems and Computers, 2010Co-Authors: Chih-wen Lu, Ching-min HsiaoAbstract:A compact high-speed low-power rail-to-rail Buffer Amplifier, which is suitable for driving heavy capacitive loads, is proposed. The Buffer Amplifier is composed of a pair of push-pull output transistors with two feedback loops consisting of a pair of complementary error Amplifiers and a pair of complementary common-source Amplifiers. The Buffer draws little current while static but has a large driving capability while transient. A mutual bias scheme is also proposed to reduce the power consumption and the die area for LCD applications. An experimental prototype Buffer Amplifier implemented in a 0.35 μm CMOS technology demonstrates that the settling time is 1.5 μs for a voltage swing of 0.1 ~ (VDD–0.1) V under a 600 pF capacitance load. Quiescent current of 4 μA is measured. The area of this Buffer is 32 × 109 μm2.
Salvatore Pennisi - One of the best experts on this subject based on the ideXlab platform.
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Dual Push–Pull High-Speed Rail-to-Rail CMOS Buffer Amplifier for Flat-Panel Displays
IEEE Transactions on Circuits and Systems Ii-express Briefs, 2018Co-Authors: A. D. Grasso, G. Palumbo, Salvatore PennisiAbstract:This brief presents the experimental validation of a low-power, large output swing, class-AB Buffer Amplifier for column drivers of active-matrix flat-panel displays. By exploiting two complementary input Amplifiers and a dual-path push–pull output stage, the proposed circuit achieves high-drive performance and rail-to-rail operation. In addition, two current boosters allow area optimization of the output diving transistors by dynamically lowering their threshold voltage. Implemented in a standard triple-well CMOS 0.35- ${\mu }{\text{m}}$ technology and supplied from a 3-V supply, the proposed Buffer Amplifier can drive a 1-nF column line load within a 1.11- ${\mu }\text{s}$ settling time under a full voltage swing, while drawing only 1.6 ${\mu }\text{A}$ quiescent current and occupying 5562 ${\mu }{\text{m}}^{{2}}$ of silicon area. As compared to the state of the art, the best figure of merit (pF/ ${\mu }\text{s}{\cdot } {\mu }\text{A}$ ) is found.
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Self-Biased Dual-Path Push-Pull Output Buffer Amplifier for LCD Column Drivers
IEEE Transactions on Circuits and Systems I: Regular Papers, 2014Co-Authors: A. D. Grasso, G. Palumbo, Davide Marano, Fermin Esparza-alfaro, Antonio J. Lopez-martin, Salvatore PennisiAbstract:A high-performance Buffer Amplifier topology for liquid crystal display drivers is presented. The proposed Amplifier achieves fast driving performance and offers a rail-to-rail common-mode input range. Enhanced slewing and settling capabilities are achieved through a novel output stage performing dual-path push-pull operation. No additional biasing network is required to set the quiescent conditions of the class-AB output stage, since the output static current is inherently controlled by the input differential stage itself, without additional power dissipation. Experimental results demonstrate that the suggested Buffer can drive a 1000-pF capacitive load with a 5.7-V/μs slew-rate and a 0.71-μs settling time, while drawing 32-μA overall quiescent current from a 5-V power supply.
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A low-quiescent current two-input/output Buffer Amplifier for LCDs
2012 IEEE International Symposium on Circuits and Systems (ISCAS), 2012Co-Authors: Chih-wen Lu, Salvatore PennisiAbstract:This study proposes a low-quiescent current two-input/output Buffer Amplifier for LCD applications. A current reuse technique is employed in the output stage of the Buffer Amplifier to reduce the quiescent current consumption. An experimental prototype 6-bit LCD column driver with the proposed Buffer Amplifiers implemented in a 0.35-μm CMOS technology demonstrates that an average value of 0.6 μA static current is consumed in one channel driver. The settling time to settle within 0.2% of the final voltage is 6 μs under a 30-KΩ-resistance and 30-pF-capacitance load. The area of this two-input/output Buffer Amplifier is 21.5 μm × 190 μm.
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a low quiescent current two input output Buffer Amplifier for lcds
International Symposium on Circuits and Systems, 2012Co-Authors: Chih-wen Lu, Salvatore PennisiAbstract:This study proposes a low-quiescent current two-input/output Buffer Amplifier for LCD applications. A current reuse technique is employed in the output stage of the Buffer Amplifier to reduce the quiescent current consumption. An experimental prototype 6-bit LCD column driver with the proposed Buffer Amplifiers implemented in a 0.35-µm CMOS technology demonstrates that an average value of 0.6 µA static current is consumed in one channel driver. The settling time to settle within 0.2% of the final voltage is 6 µs under a 30-KΩ-resistance and 30-pF-capacitance load. The area of this two-input/output Buffer Amplifier is 21.5 µm × 190 µm.
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ISCAS - A low-quiescent current two-input/output Buffer Amplifier for LCDs
2012 IEEE International Symposium on Circuits and Systems, 2012Co-Authors: Chih-wen Lu, Salvatore PennisiAbstract:This study proposes a low-quiescent current two-input/output Buffer Amplifier for LCD applications. A current reuse technique is employed in the output stage of the Buffer Amplifier to reduce the quiescent current consumption. An experimental prototype 6-bit LCD column driver with the proposed Buffer Amplifiers implemented in a 0.35-µm CMOS technology demonstrates that an average value of 0.6 µA static current is consumed in one channel driver. The settling time to settle within 0.2% of the final voltage is 6 µs under a 30-KΩ-resistance and 30-pF-capacitance load. The area of this two-input/output Buffer Amplifier is 21.5 µm × 190 µm.
G. Palumbo - One of the best experts on this subject based on the ideXlab platform.
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dual push pull high speed rail to rail cmos Buffer Amplifier for flat panel displays
IEEE Transactions on Circuits and Systems Ii-express Briefs, 2018Co-Authors: A. D. Grasso, G. Palumbo, S. PennisiAbstract:This brief presents the experimental validation of a low-power, large output swing, class-AB Buffer Amplifier for column drivers of active-matrix flat-panel displays. By exploiting two complementary input Amplifiers and a dual-path push–pull output stage, the proposed circuit achieves high-drive performance and rail-to-rail operation. In addition, two current boosters allow area optimization of the output diving transistors by dynamically lowering their threshold voltage. Implemented in a standard triple-well CMOS 0.35- ${\mu }{\text{m}}$ technology and supplied from a 3-V supply, the proposed Buffer Amplifier can drive a 1-nF column line load within a 1.11- ${\mu }\text{s}$ settling time under a full voltage swing, while drawing only 1.6 ${\mu }\text{A}$ quiescent current and occupying 5562 ${\mu }{\text{m}}^{{2}}$ of silicon area. As compared to the state of the art, the best figure of merit (pF/ ${\mu }\text{s}{\cdot } {\mu }\text{A}$ ) is found.
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Dual Push–Pull High-Speed Rail-to-Rail CMOS Buffer Amplifier for Flat-Panel Displays
IEEE Transactions on Circuits and Systems Ii-express Briefs, 2018Co-Authors: A. D. Grasso, G. Palumbo, Salvatore PennisiAbstract:This brief presents the experimental validation of a low-power, large output swing, class-AB Buffer Amplifier for column drivers of active-matrix flat-panel displays. By exploiting two complementary input Amplifiers and a dual-path push–pull output stage, the proposed circuit achieves high-drive performance and rail-to-rail operation. In addition, two current boosters allow area optimization of the output diving transistors by dynamically lowering their threshold voltage. Implemented in a standard triple-well CMOS 0.35- ${\mu }{\text{m}}$ technology and supplied from a 3-V supply, the proposed Buffer Amplifier can drive a 1-nF column line load within a 1.11- ${\mu }\text{s}$ settling time under a full voltage swing, while drawing only 1.6 ${\mu }\text{A}$ quiescent current and occupying 5562 ${\mu }{\text{m}}^{{2}}$ of silicon area. As compared to the state of the art, the best figure of merit (pF/ ${\mu }\text{s}{\cdot } {\mu }\text{A}$ ) is found.
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Dual Push–Pull High-Speed Rail-to-Rail CMOS Buffer Amplifier for Flat-Panel Displays
IEEE Transactions on Circuits and Systems II: Express Briefs, 2018Co-Authors: A. D. Grasso, G. Palumbo, S. PennisiAbstract:This brief presents the experimental validation of a low-power, large output swing, class-AB Buffer Amplifier for column drivers of active-matrix flat-panel displays. By exploiting two complementary input Amplifiers and a dual-path push- pull output stage, the proposed circuit achieves high-drive performance and rail-to-rail operation. In addition, two current boosters allow area optimization of the output diving transistors by dynamically lowering their threshold voltage. Implemented in a standard triple-well CMOS 0.35-μm technology and supplied from a 3-V supply, the proposed Buffer Amplifier can drive a 1-nF column line load within a 1.11-μs settling time under a full voltage swing, while drawing only 1.6 μA quiescent current and occupying 5562 μm2 of silicon area. As compared to the state of the art, the best figure of merit (pF/μs·μA) is found.
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Self-Biased Dual-Path Push-Pull Output Buffer Amplifier for LCD Column Drivers
IEEE Transactions on Circuits and Systems I: Regular Papers, 2014Co-Authors: A. D. Grasso, G. Palumbo, Davide Marano, Fermin Esparza-alfaro, Antonio J. Lopez-martin, Salvatore PennisiAbstract:A high-performance Buffer Amplifier topology for liquid crystal display drivers is presented. The proposed Amplifier achieves fast driving performance and offers a rail-to-rail common-mode input range. Enhanced slewing and settling capabilities are achieved through a novel output stage performing dual-path push-pull operation. No additional biasing network is required to set the quiescent conditions of the class-AB output stage, since the output static current is inherently controlled by the input differential stage itself, without additional power dissipation. Experimental results demonstrate that the suggested Buffer can drive a 1000-pF capacitive load with a 5.7-V/μs slew-rate and a 0.71-μs settling time, while drawing 32-μA overall quiescent current from a 5-V power supply.
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Self-biased dual-path push-pull output Buffer Amplifier topology for LCD driver applications
2011 IEEE International Symposium of Circuits and Systems (ISCAS), 2011Co-Authors: Davide Marano, G. Palumbo, Salvatore PennisiAbstract:The present paper addresses an improved and compact low-power high-speed Buffer Amplifier topology for large size liquid crystal display drivers. The proposed Buffer achieves fast driving performance, draws a low quiescent current and offers a rail-to-rail common-mode input range. The circuit provides enhanced slewing and settling capabilities by realizing a dual-path push-pull operation of the output stage. No additional bias network is required to fix the quiescent conditions of the class-AB output stage, since the output static current is inherently controlled by the input differential stage itself without auxiliary power dissipation. Simulation results demonstrate that the suggested Buffer can drive a 1000-pF column line capacitive load with a 5.8-V/μs slew-rate and a 0.75-μs settling time, while drawing only 3-μA quiescent current from a 3-V power supply.
M. Shridhar - One of the best experts on this subject based on the ideXlab platform.
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A LARGE-SWING HIGH-DRIVE CMOS Buffer Amplifier FOR A WIDE LOAD RANGE
Journal of Circuits Systems and Computers, 1992Co-Authors: N. Yazdi, M. Ahmadi, G.a. Jullien, M. ShridharAbstract:A high-swing, high-drive CMOS Buffer Amplifier, with good stability over a wide range of capacitive and resistive loads, is presented in this paper. A new area efficient output stage with a relatively small compensation capacitor has been used so that the circuit occupies only 120 mils2 in a 3 μm CMOS technology. The Buffer has a drive capability of 110 kHz into a 5000 pF load with a rail-to-rail output swing for load resistances greater than 10 kΩ and acceptable total harmonic distortion with loads down to 270 Ω.
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A high-dynamic range CMOS Buffer Amplifier with high-drive capability
[Proceedings] 1992 IEEE International Symposium on Circuits and Systems, 1992Co-Authors: N. Yazdi, M. Ahmadi, G.a. Jullien, M. ShridharAbstract:A high-swing, high-drive CMOS Buffer Amplifier with a good stability over a wide range of capacitive and resistive loads is presented. A new area efficient output stage with a relatively small compensation capacitor has been used. The Buffer was designed as a standard cell for analog and mixed mode VLSI applications and the current implementation is in a standard 3- mu m p-well CMOS process. Simulations revealed a drive capability of 140 kHz into a 5000-pF load. The Buffer has rail to rail output drive for resistive loads greater than 10 k Omega . The Buffer had acceptable total harmonic distribution with loads down to 270 Omega .
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A high-drive, high-swing Buffer Amplifier
1991. IEEE International Sympoisum on Circuits and Systems, 1991Co-Authors: A. Nosratinia, M. Ahmadi, G.a. Jullien, M. ShridharAbstract:A CMOS high dynamic range, high-drive Buffer suitable for driving large capacitive loads is presented. A new area-efficient output stage has been used so that simulations reveal a drive capability of 200 kHz into a 5000-pF load. The circuit occupies only 110 mils/sup 2/ in a 3- mu m technology. The output range is rail to rail for R>10 k Omega . The Buffer is capable of driving resistive loads down to 300 Omega with acceptable total harmonic distortion (THD).
Davide Marano - One of the best experts on this subject based on the ideXlab platform.
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Self-Biased Dual-Path Push-Pull Output Buffer Amplifier for LCD Column Drivers
IEEE Transactions on Circuits and Systems I: Regular Papers, 2014Co-Authors: A. D. Grasso, G. Palumbo, Davide Marano, Fermin Esparza-alfaro, Antonio J. Lopez-martin, Salvatore PennisiAbstract:A high-performance Buffer Amplifier topology for liquid crystal display drivers is presented. The proposed Amplifier achieves fast driving performance and offers a rail-to-rail common-mode input range. Enhanced slewing and settling capabilities are achieved through a novel output stage performing dual-path push-pull operation. No additional biasing network is required to set the quiescent conditions of the class-AB output stage, since the output static current is inherently controlled by the input differential stage itself, without additional power dissipation. Experimental results demonstrate that the suggested Buffer can drive a 1000-pF capacitive load with a 5.7-V/μs slew-rate and a 0.71-μs settling time, while drawing 32-μA overall quiescent current from a 5-V power supply.
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Self-biased dual-path push-pull output Buffer Amplifier topology for LCD driver applications
2011 IEEE International Symposium of Circuits and Systems (ISCAS), 2011Co-Authors: Davide Marano, G. Palumbo, Salvatore PennisiAbstract:The present paper addresses an improved and compact low-power high-speed Buffer Amplifier topology for large size liquid crystal display drivers. The proposed Buffer achieves fast driving performance, draws a low quiescent current and offers a rail-to-rail common-mode input range. The circuit provides enhanced slewing and settling capabilities by realizing a dual-path push-pull operation of the output stage. No additional bias network is required to fix the quiescent conditions of the class-AB output stage, since the output static current is inherently controlled by the input differential stage itself without auxiliary power dissipation. Simulation results demonstrate that the suggested Buffer can drive a 1000-pF column line capacitive load with a 5.8-V/μs slew-rate and a 0.75-μs settling time, while drawing only 3-μA quiescent current from a 3-V power supply.
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improved low power high speed Buffer Amplifier with slew rate enhancement for lcd applications
Journal of Circuits Systems and Computers, 2010Co-Authors: Davide Marano, G. Palumbo, S. PennisiAbstract:The present paper addresses an improved low-power high-speed Buffer Amplifier topology for large-size liquid crystal display applications. The proposed Buffer achieves high-speed driving performance while drawing a low quiescent current during static operation. The circuit offers enhanced slewing capabilities with a limited power consumption by exploiting a slew detector which monitors the output voltage of the input differential Amplifier and outputs an additional current signal providing slew-rate enhancement at the output stage. Post-layout simulations show that the proposed Buffer can drive a 1 nF column line load with 8.5 V/μs slew-rate and 0.8 μs settling time, while drawing only 8 μA static current from a 3 V power supply.
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Low-power dual-active class-AB Buffer Amplifier with self-biasing network for LCD column drivers
Proceedings of 2010 IEEE International Symposium on Circuits and Systems, 2010Co-Authors: Davide Marano, G. Palumbo, Salvatore PennisiAbstract:This work addresses a new compact low-power highspeed output Buffer Amplifier topology for large-size LCD applications. The suggested Buffer achieves fast driving performance, draws a low quiescent current during static operation and offers a rail-to-rail common-mode input range. The circuit provides enhanced slewing capabilities by exploiting the push-pull output sections of two basic complementary-type input Amplifiers to realize a dual-path push-pull operation of the output stage. An auxiliary bias network integrated in the input differential stage allows the quiescent conditions of the class-AB output stage to be inherently controlled without additional power dissipation. Post-layout results confirm that the proposed Amplifier can drive a 1-nF capacitive load within a 0.9-μs settling time under a 3-V full voltage swing, while drawing only 3.5-μA quiescent current.
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A novel low-power high-speed rail-to-rail class-B Buffer Amplifier for LCD output drivers
Proceedings of 2010 IEEE International Symposium on Circuits and Systems, 2010Co-Authors: Davide Marano, G. Palumbo, Salvatore PennisiAbstract:This paper addresses a new compact low-power class-B Buffer Amplifier topology for large-size liquid crystal display applications. The proposed Buffer achieves high-speed driving performance, draws a low quiescent current during static operation and offers a rail-to-rail common-mode input range. The circuit provides enhanced slewing capabilities with a limited power consumption by exploiting two current comparators embodied in the input stage, which sense the input signal transients to turn on the output stage transistors. A rail-to-rail stacked mirror differential Amplifier is used to amplify the input signal difference and supply the bias voltages for the output stage. Simulation results show that the proposed Buffer can drive a 1-nF column line load within 1.8-μs settling time under a full voltage swing, while drawing only 3.5-μA static current from a 3-V power supply.
