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S K Mitra - One of the best experts on this subject based on the ideXlab platform.
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two stage cic based Decimator with improved characteristics
Iet Signal Processing, 2010Co-Authors: Jovanovic G Dolecek, S K MitraAbstract:A simple two-stage multiplierless cascaded-integrator-comb (CIC)-based Decimator is presented. The first stage is a cascaded CIC filter whereas the second stage is a cascaded CIC filter and a second-order multiplierless compensator. The proposed Decimator can be realised without filtering at high input rate by making use of the polyphase decomposition of the comb filter in the first stage. The proposed filter exhibits high aliasing attenuation and a low passband droop. The design parameters are the decimation factors, M 1 and M 2 , numbers of cascaded CIC filters L and K , and parameter b of the compensator.
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efficient multistage comb modified rotated sinc rs Decimator
European Signal Processing Conference, 2004Co-Authors: G Jovanovicdolecek, S K MitraAbstract:This paper presents a new multistage comb-rotated sinc (RS) Decimator. The proposed structure consists of different cascaded comb sections, each down-sampled by a specific down-sampling factor. The number of sections depends on the decimation factor of the original comb Decimator. The first section is realized in a non-recursive form. Using the polyphase decomposition, the sub-filters of the first section can be operated at lower rate which depends on the down-sampling factor of the first section. Additionally, the rotated sinc (RS) filter is cascaded in the second section, thus permitting both multipliers of the RS filter to work at the lower rate. The magnitude response of the proposed structure is better than that of the original comb Decimator.
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efficient comb rotated sinc rs Decimator with sharpened magnitude response
Midwest Symposium on Circuits and Systems, 2004Co-Authors: Gordana Jovanovic Dolecek, S K MitraAbstract:This paper presents a comb-rotated sine (RS) Decimator with a sharpened magnitude response. The Decimator is composed of two main sections. The first section is a cascaded comb Decimator, while the second section is a cascade of a sharpened comb and a rotated sine (RS) Decimator. Using the polyphase decomposition, the subfilters of the first section can be operated at lower rate, which depends on the down-sampling factor of the first section. Additionally, as the RS filter is in the second section, both multipliers of the RS filter work at the lower rate. The magnitude response of the proposed filter is improved by using the sharpened technique in the second section.
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sharpened comb Decimator with improved magnitude response
International Conference on Acoustics Speech and Signal Processing, 2004Co-Authors: G Jovanovicdolecek, S K MitraAbstract:A new structure for the realization of a comb decimation filter with a sharpened magnitude response is advanced. The proposed structure consists of two main sections: a comb section and a sharpening comb section with the latter section operating at a lower rate than the high input rate. Using a polyphase decomposition, the sub-filters of the first section can also be operated at this lower rate. The improved magnitude response has been obtained by using the filter sharpening approach of J.F. Kaiser and R.W. Hamming (see IEEE Trans. on Acoustics, Speech, and Sig. Process., vol.ASSP25, p.415-22, 1977). The proposed filter has much less passband droop and better attenuation than the equivalent comb filter.
Sanjit K. Mitra - One of the best experts on this subject based on the ideXlab platform.
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EFFICIENT MULTISTAGE COMB-MODIFIED ROTATED SINC (RS) Decimator
2014Co-Authors: Gordana Jovanovic-dolecek, Sanjit K. MitraAbstract:This paper presents a new multistage comb-rotated sinc (RS) Decimator. The proposed structure consists of different cascaded comb sections, each down-sampled by a specific down-sampling factor. The number of sections depends on the decimation factor of the original comb Decimator. The first section is realized in a non-recursive form. Using the polyphase decomposition, the sub-filters of the first section can be operated at lower rate which depends on the down-sampling factor of the first section. Additionally, the rotated sinc (RS) filter is cascaded in the second section, thus permitting both multipliers of the RS filter to work at the lower rate. The magnitude response of the proposed structure is better than that of the original comb Decimator. Figure 1: CIC decimation filter The above decimation filter is attractive in many applications because of its very low complexity. It should be noted that while the differentiator section operates at the lower data rate, the integrator section works at the higher input data rate resulting in a larger chip area and a higher power consumption especially when the decimation factor and the filter order are high [3]. The use of a non-recursive equivalent to Eq. (1) reduces power consumption and increases the circuit speed [3-5]. More details on a comparison of the performances of the recursive and non-recursive implementation are given in [3]. In this paper we propose a new multistage structure in which the first stage is implemented non-recursively while all other stages are implemented recursively. The magnitude response of this structure is improved over that of the original comb filter by using a modified rotated sinc (RS) filter introduced in [6]. Unlike the structure advanced in [6], where one multiplier works at the high input rate, in the structure proposed in this paper, both multipliers work at the lower rate
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Novel Two-Stage Comb Decimator
2012Co-Authors: Gordana Jovanovic Dolecek, Sanjit K. MitraAbstract:A simple method for the design of a multiplier-less comb-based decimation filter is presented. The filter compensates the comb passband droop, and has the desired attenuation in the first folding band. The proposed structure has two decimation stages, both with simpler comb filters. The desired attenuation in the first folding band is achieved by an appropriate number of cascaded combs in the second stage. A simple compensation filter, working at a low output rate, provides the desired compensation in the pass band. The choice of the design parameters is presented along with a comparison of the proposed method to some other existing design methods. Keyword. Comb filter, decimation, folding bands, compensation.
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Non-recursive decimation filters with arbitrary integer decimation factors
IET Circuits Devices & Systems, 2012Co-Authors: Kalyan Mondal, Sanjit K. MitraAbstract:Cascaded integrator comb (CIC) filters are in wide use in oversampled analog-to-digital converters. In this study, the authors advances three new cascaded Decimator structures with integer coefficients designed using a polynomial factorisation approach. Each one of the designed Decimators shows better stopband attenuation for a given order and decimation factor than the CIC or recently proposed generalised comb filter (GCF) and may not require any prefilter for performance enhancement. A fourth new Decimator structure is a hybrid between the CIC and GCF with coefficients approximated by integers. Decimator power dissipation analysis and optimisation have previously been done either by counting the number of additions per sample rate or by focusing on register clock distribution. The authors propose a new metric for estimating the power dissipation of a filter structure from its architecture accounting for dissipation both in the adder cells and the flip-flops. The authors show frequency domain characteristics and compare power dissipations of all the new structures using a representative example.
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A new two-stage sharpened comb Decimator
IEEE Transactions on Circuits and Systems I: Regular Papers, 2005Co-Authors: Gordana Jovanovic-dolecek, Sanjit K. MitraAbstract:This paper presents a new sharpened comb Decimator structure consisting of a cascade of a comb-filter based Decimator and a sharpened comb Decimator. The proposed realization scheme allows the sharpened section to operate at a lower rate that depends on the decimation factor of the first section. Using a polyphase decomposition, the subfilters of the first section can also be operated at this lower rate.
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Structural subband decomposition: a new concept in digital signal processing
ISPA 2001. Proceedings of the 2nd International Symposium on Image and Signal Processing and Analysis. In conjunction with 23rd International Conferen, 2001Co-Authors: Sanjit K. MitraAbstract:Summary form only given, as follows. Polyphase decomposition of a sequence was advanced to develop computationally efficient interpolators and Decimators, and has also been used to design computationally efficient quadrature-mirror filter banks. The polyphase decomposition represents a sequence into a set of sub-sequences, called polyphase components. However, the polyphase components do not exhibit any spectral separation. In this presentation, we first review the concept of structural subband decomposition, generalization of the polyphase decomposition, which decomposes a sequence into a set of sub-sequences with some spectral separation that can be exploited advantageously in many digital signal processing applications. We then outline some of the applications of the structural subband decomposition, such as efficient design and implementation of FIR digital filters, development of computationally efficient Decimators and interpolators, subband adaptive filtering, and fast computation of discrete transforms.
G Jovanovicdolecek - One of the best experts on this subject based on the ideXlab platform.
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efficient multistage comb modified rotated sinc rs Decimator
European Signal Processing Conference, 2004Co-Authors: G Jovanovicdolecek, S K MitraAbstract:This paper presents a new multistage comb-rotated sinc (RS) Decimator. The proposed structure consists of different cascaded comb sections, each down-sampled by a specific down-sampling factor. The number of sections depends on the decimation factor of the original comb Decimator. The first section is realized in a non-recursive form. Using the polyphase decomposition, the sub-filters of the first section can be operated at lower rate which depends on the down-sampling factor of the first section. Additionally, the rotated sinc (RS) filter is cascaded in the second section, thus permitting both multipliers of the RS filter to work at the lower rate. The magnitude response of the proposed structure is better than that of the original comb Decimator.
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sharpened comb Decimator with improved magnitude response
International Conference on Acoustics Speech and Signal Processing, 2004Co-Authors: G Jovanovicdolecek, S K MitraAbstract:A new structure for the realization of a comb decimation filter with a sharpened magnitude response is advanced. The proposed structure consists of two main sections: a comb section and a sharpening comb section with the latter section operating at a lower rate than the high input rate. Using a polyphase decomposition, the sub-filters of the first section can also be operated at this lower rate. The improved magnitude response has been obtained by using the filter sharpening approach of J.F. Kaiser and R.W. Hamming (see IEEE Trans. on Acoustics, Speech, and Sig. Process., vol.ASSP25, p.415-22, 1977). The proposed filter has much less passband droop and better attenuation than the equivalent comb filter.
Gordana Jovanovic Dolecek - One of the best experts on this subject based on the ideXlab platform.
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NOVEL SHARPENED COMPENSATED COMB Decimator
2014Co-Authors: Gordana Jovanovic Dolecek, Vlatko Doleček, Bosna HerzegovinaAbstract:This paper presents the novel comb Decimator. The method is based on the pass band comb compensation and the sharpening technique. The compensator is the simple multiplier less filter which can be moved to a lower rate which is M times less than the high input rate where M is the decimation factor. The parameters of compensator are independent of the decimation factor. The resulting filter is the multiplier less filter and exhibits the significantly decreased pass band droop, as well as the increased attenuation in the folding bands, compared with the corresponding comb filter
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power and area efficient comb based Decimator for sigma delta adcs with high decimation factors
International Symposium on Circuits and Systems, 2013Co-Authors: Gerardo Molina Salgado, Gordana Jovanovic Dolecek, Jose M De La RosaAbstract:This paper introduces a power and area efficient comb-based decimation structure, particularly suited for high values of decimation factors which are a power of two. The proposed topology has two stages, where the first stage is in a non-recursive form and the second one is in a recursive form (CIC filter). Moreover, a slight modification of the proposed Decimator structure is presented in order to obtain an improved alias rejection. Simulation results are shown to validate the proposed approach.
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ISCAS - Power and area efficient comb-based Decimator for Sigma-Delta ADCs with high decimation factors
2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013Co-Authors: Gerardo Molina Salgado, Gordana Jovanovic Dolecek, Jose M De La RosaAbstract:This paper introduces a power and area efficient comb-based decimation structure, particularly suited for high values of decimation factors which are a power of two. The proposed topology has two stages, where the first stage is in a non-recursive form and the second one is in a recursive form (CIC filter). Moreover, a slight modification of the proposed Decimator structure is presented in order to obtain an improved alias rejection. Simulation results are shown to validate the proposed approach.
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Novel Two-Stage Comb Decimator
2012Co-Authors: Gordana Jovanovic Dolecek, Sanjit K. MitraAbstract:A simple method for the design of a multiplier-less comb-based decimation filter is presented. The filter compensates the comb passband droop, and has the desired attenuation in the first folding band. The proposed structure has two decimation stages, both with simpler comb filters. The desired attenuation in the first folding band is achieved by an appropriate number of cascaded combs in the second stage. A simple compensation filter, working at a low output rate, provides the desired compensation in the pass band. The choice of the design parameters is presented along with a comparison of the proposed method to some other existing design methods. Keyword. Comb filter, decimation, folding bands, compensation.
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comb based Decimator for sdr applications
International Conference on Communications, 2010Co-Authors: Gordana Jovanovic DolecekAbstract:This paper presents a novel comb-based Decimator for the SDR (Software Defined Radio) applications. The expanded cosine filters and the expanded multiplierless compensators are cascaded with the comb filter. The comb filter is realized in a nonrecursive form. We consider the case where the decimation factor M is the power of two, i.e M=2k. In that way we have k+1-stage structure, where the first k stages are the cosine filters followed by the downsampling by two, and the last stage is the cascade of simple compensators. The proposed structure has much better magnitude characteristic than the corresponding comb filter.
Rajesh Mehra - One of the best experts on this subject based on the ideXlab platform.
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fpga based multiplier less Decimator for wireless communication systems
2020 International Conference on Computation Automation and Knowledge Management (ICCAKM), 2020Co-Authors: Rajesh Mehra, Lajwanti SinghAbstract:Reconfigurable high speed and area efficient reconfigurable Decimator is presented for wireless communication systems. The multiplier less Distributed Arithmetic (DA) Algorithm is used to achieve better speed by consuming fewer resources. The proposed Decimator is designed using Polyphase decomposition technique. It is further supplemented by optimized Look up Table (LUT) partitioning to reduce hardware complexity. The developed Decimator is simulated and synthesized on Virtex 2Pro based target Field Programmable Gate Array(FPGA). The proposed Decimator shows an improvement of 0.5-9.6% in speed. The design is also consuming 5.21-12.69% less slices, 12.54% less F/Flops and 4.34-10.50% less LUTs for economical solution.
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for Enhanced Resource Utilization
2015Co-Authors: Rajesh Mehra, S S PattnaikAbstract:In this paper a hybrid approach is presented to design and implement a GSM digital down convertor for enhanced resource utilization. The proposed DDC has been implemented by hybridizing the multiplier less and multiplier based Decimators. A multiplier less CIC Decimator has been used to reduce the cost by reducing the multiplier requirement. Two computationally efficient equiripple polyphase decomposition structure based Decimators have been to reduce the filter order and hardware complexity. The embedded multipliers, LUTs and BRAMs have been efficiently utilized to enhance the system performance and resource utilization. The proposed GSM DDC has been designed and simulated Matlab and Simulink, synthesized with Xilinx Synthesis Tool and implemented on Virtex-II Pro based xc2vp20 FPGA device. The proposed design has shown a minimum period of 159.96 MHz with enhance resource utilization ranging from 4-12 % in terms slices, flip flops LUTs, BRAMs and multipliers
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Optimized Design of CIC Decimator using Embedded LUTs of FPGA for Wireless Communication Systems
2015Co-Authors: Rajesh Mehra, Swapna DeviAbstract:Abstract—In this paper an efficient multiplier less technique is presented to design a high speed CIC Decimator for wireless applications like SDR and GSM. The implementation is based on efficient utilization of embedded LUTs of target device to enhance the speed of proposed design. It is an efficient method because the use of embedded LUTs not only increases the speed but also saves the resources on the target device. The fully pipelined CIC Decimator is designed with Matlab, simulated with Modelsim, synthesized with Xilinx Synthesis Tool (XST), and implemented on Spartan-3E based XC3s500e-4fg320 target device. The proposed design can be operated at an estimated frequency of 206.2 MHz by consuming considerably less available resources of target device to provide cost effective solution for SDR applications. The power consumption of the proposed design is 0.08098W at 27.1°C junction temperature. Keywords—ASIC, CIC, FPGA, GSM, SD
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FPGA-Based Design of High-Speed CIC Decimator for Wireless Applications
2015Co-Authors: Rajesh Mehra, Rashmi AroraAbstract:Abstract — In this paper an efficient multiplier-less technique is presented to design and implement a high speed CIC Decimator for wireless applications like SDR and GSM. The Cascaded Integrator Comb is a commonly used decimation filter which performs sample rate conversion (SRC) using only additions/subtractions. The implementation is based on efficient utilization of embedded LUTs of the target device to enhance the speed of proposed design. It is an efficient method used to design and implement CIC Decimator because the use of embedded LUTs not only increases the speed but also saves the resources on the target device. The fully pipelined CIC Decimator is designed with Matlab, simulated with Xilinx AccelDSP, synthesized with Xilinx Synthesis Tool (XST), and implemented on Virtex-II based XC2VP50-6 target FPGA device. The proposed design can operate at an estimated frequency of 276.6 MHz by consuming considerably less resources on target device to provide cost effective solution for SDR based wireless applications. Keywords- CIC; FPGA; FPGA; GSM; LUT; SDR. I
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FPGA based Speed Efficient Decimator using Distributed Arithmetic Algorithm
2014Co-Authors: Rajesh Mehra, Lajwanti SinghAbstract:In this paper, an efficient FPGA implementation of a multipliers less Decimator is presented for wireless application. DA has been used to implement a Decimator taking advantage of embedded LUT based structure of FPGAs. Speed and area efficient solution is designed using half band polyphase decomposition FIR structure. The proposed Decimator has been designed with MATLAB and synthesized with Xilinx synthesis tool (XST)10.1 and implemented on Spartan-3E based 3s500efg.320-4 FPGA device. Improvement of 28 % in speed and 50 % in area has been observed as compared to MAC based approach
