The Experts below are selected from a list of 76809 Experts worldwide ranked by ideXlab platform

Rolf Drechsler - One of the best experts on this subject based on the ideXlab platform.

  • towards generation of a programmable power management unit at the Electronic System Level
    Design and Diagnostics of Electronic Circuits and Systems, 2020
    Co-Authors: David Lemma, Daniel Grose, Mehran Goli, Rolf Drechsler
    Abstract:

    Power-awareness is now crucial in the design flow for System-on-Chip (SoC) development. The main objective of power-awareness is to implement a Power Management Strategy (PMS) for the SoC by generating a flexible, yet efficient Power Management Unit (PMU). As the cost of structural changes to a design increases in advanced stages of development, the PMU should be incorporated into the design as early as possible. At early stages, Virtual Prototype (VP) based design at the Electronic System Level (ESL) has become an industry accepted solution. However, existing methods focusing on generating a PMU at the ESL have several drawbacks, such as relying on designers’ domain expertise, a low degree of automation and a lack of programmability.This paper introduces a novel approach that automatically generates a programmable PMU for a given VP at the ESL without the need for prior knowledge about the VP’s structure and behavior. Our approach consists of three main phases: activity pattern extraction, power-aware analysis, and PMU generation. The programmability feature of the generated PMU enables designers to support various target applications. The efficiency and flexibility of the proposed approach are evaluated by the power consumption reduction enabled by the PMU within a real-world VP-based SoC platform.

  • automated nonintrusive analysis of Electronic System Level designs
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2020
    Co-Authors: Mehran Goli, Jannis Stoppe, Rolf Drechsler
    Abstract:

    Due to the ever increasing complexity of hardware Systems, designers strive for higher Levels of abstractions in the early stages of the design process. Modeling hardware at the Electronic System Level (ESL) is one way to address this demand, with the C++-based System modeling framework SystemC and its abstract communication library transaction Level modeling (TLM) having become de-facto standards for ESL System design. While the C++ compiler is sufficient to compile and simulate a given ESL design, for tasks of design understanding, debugging, or validation (where access to the details of design’s structure and behavior is necessarily required), design needs to be processed by an appropriate tool. This problem is often solved by adding instrumentation code to either the design or the library, usually resulting in incomplete logs, work overhead and/or incompatibilities. This paper introduces an approach that automatically extracts information about both, structure and behavior of SystemC designs and TLM transactions, nonintrusively. The information is retrieved from a given design by running it in debug mode while being connected to a preprogrammed debugger, thus leaving the existing sources and workflows untouched while collecting a vast amount of data without user intervention. Illustrating use cases, value change dump files of the SystemC models’ behavior and unified modeling language activity diagrams of transaction protocols are created automatically from simulation runs.

  • automated analysis of virtual prototypes at Electronic System Level
    Great Lakes Symposium on VLSI, 2019
    Co-Authors: Mehran Goli, Muhammad Hassan, Daniel Grose, Rolf Drechsler
    Abstract:

    The exponential increase in functionality of System-on-Chips (SoCs) and reduced Time-to-Market (TTM) requirements have significantly altered the typical design and verification flow. Virtual Prototyping (VP) at the Electronic System Level (ESL) using SystemC and its Transaction Level Modeling (TLM) framework is an industry-accepted solution. VP design exploration, review, debugging, and integration of ever changing functional requirements can be made faster with the help of design understanding and visualization methods. Hence, in this paper, we propose a fully automated structural, and behavioral analysis approach for visualization of ESL VPs including TLM-2.0 VPs. At the heart of the analysis is a hybrid approach which uses static and dynamic methods to extract structural and behavioral information of the VP. Afterwards, the extracted information is translated into structural and graphical representations such as UML diagrams (specifying TLM-2.0 transactions' protocols), and XML format (describing designs' structure). Experimental results including a real-world VP shows the effectiveness of our approach.

  • automatic protocol compliance checking of Systemc tlm 2 0 simulation behavior using timed automata
    International Conference on Computer Design, 2017
    Co-Authors: Mehran Goli, Jannis Stoppe, Rolf Drechsler
    Abstract:

    The increasing complexity of todays digital circuit designs led to the increased usage of abstract models. In particular, the Electronic System Level (ESL) has emerged as an area of active research. For ESL design, SystemC and its Transaction Level Modeling (TLM) framework have become the standard tools for abstract modeling. The resulting models represent both, an executable specification and a reference model for the hardware design. The correctness of these designs is important as undetected errors may propagate to less abstract Levels in the design process, increasing the potential amount of work required to fix them. To quickly ensure that implementations and reference emit the same behavior, the comparison between these abstractions needs to be both, flexible and automated. This paper presents a method to verify the simulation behavior of a given System TLM-2.0 design against TLM-2.0 protocols. The System's structural description and its run-time behavior are translated to a single, consistent formal model. This is then used to verify that a simulation run adheres to a given protocol. The protocol compliance checks are performed using the UPPAAL model checker and applied to several TLM models.

  • automatic equivalence checking for Systemc tlm 2 0 models against their formal specifications
    Design Automation and Test in Europe, 2017
    Co-Authors: Mehran Goli, Jannis Stoppe, Rolf Drechsler
    Abstract:

    The necessity to handle the increasing complexity of digital circuits has led to the usage of more and more abstract design paradigms. In particular, the Electronic System Level (ESL) has become an area of active research and industrial application, especially via SystemC and its Transaction Level Modeling (TLM) framework. Additionally, the usage of formal specification languages such as the Unified Modeling Language (UML) prior to the implementation (even at higher abstraction Levels) is now a broadly accepted workflow. Utilizing this layered approach leaves the translation from the specification to the implementation to the designer, leaving the question unanswered how the equivalence of these should be verified. This paper proposes a novel, non-intrusive and broadly applicable approach to automatically validate the equivalence of the structural and behavioral information of a SystemC-TLM 2.0 model and its formal specification.

Weiwei Chen - One of the best experts on this subject based on the ideXlab platform.

  • Advances in Parallel Discrete Event Simulation for Electronic System-Level Design
    IEEE Design & Test, 2013
    Co-Authors: Weiwei Chen, Che-wei Chang, Rainer Domer
    Abstract:

    Editors' notes: The authors target the speeding up of parallel discrete event simulations in transaction-Level models.

  • Out-of-order parallel simulation for ESL design
    2012 Design Automation & Test in Europe Conference & Exhibition (DATE), 2012
    Co-Authors: Weiwei Chen, Rainer Domer
    Abstract:

    At the Electronic System Level (ESL), design validation often relies on discrete event (DE) simulation. Recently, parallel simulators have been proposed which increase simulation speed by using multiple cores available on today's PCs. However, the total order of time in DE simulation is a bottleneck that severely limits the benefits of parallel simulation. This paper presents a new out-of-order simulator for multi-core parallel DE simulation of hardware/software designs at any abstraction Level. By localizing the simulation time and carefully handling events at different times, a System model can be simulated following a partial order of time. Subject to automatic static data analysis at compile time and table-based decisions at run time, threads can be issued early which reduces the idle time of available cores. Our experiments show high performance gains in simulation speed with only a small increase of compile time.

  • Parallel discrete event simulation of Transaction Level Models
    17th Asia and South Pacific Design Automation Conference, 2012
    Co-Authors: Rainer Domer, Weiwei Chen
    Abstract:

    Describing Multi-Processor Systems-on-Chip (MPSoC) at the abstract Electronic System Level (ESL) is one task, validating them efficiently is another. Here, fast and accurate System-Level simulation is critical. Recently, Parallel Discrete Event Simulation (PDES) has gained significant attraction again as it promises to utilize the existing parallelism in today's multicore CPU hosts. This paper discusses the parallel simulation of Transaction-Level Models (TLMs) described in System-Level Description Languages (SLDLs), such as SystemC and SpecC.We review how PDES exploits the explicit parallelism in the ESL design models and uses the parallel processing units available on multicore host PCs to significantly reduce the simulation time. We show experimental results for two highly parallel benchmarks as well as for two actual embedded applications.

Rainer Domer - One of the best experts on this subject based on the ideXlab platform.

  • introduction to hardware software codesign
    Handbook of Hardware Software Codesign, 2017
    Co-Authors: Soonhoi Ha, Aviral Shrivastava, Michael Glas, Christian Haubelt, Petru Eles, Tulika Mitra, Andreas Gerstlauer, Rainer Domer, Jurgen Teich, Shuvra S. Bhattacharyya
    Abstract:

    Hardware/Software Codesign (HSCD) is an integral part of modern Electronic System Level (ESL) design flows. This chapter will review important aspects of hardware/software codesign flows, summarize ...

  • Advances in Parallel Discrete Event Simulation for Electronic System-Level Design
    IEEE Design & Test, 2013
    Co-Authors: Weiwei Chen, Che-wei Chang, Rainer Domer
    Abstract:

    Editors' notes: The authors target the speeding up of parallel discrete event simulations in transaction-Level models.

  • Out-of-order parallel simulation for ESL design
    2012 Design Automation & Test in Europe Conference & Exhibition (DATE), 2012
    Co-Authors: Weiwei Chen, Rainer Domer
    Abstract:

    At the Electronic System Level (ESL), design validation often relies on discrete event (DE) simulation. Recently, parallel simulators have been proposed which increase simulation speed by using multiple cores available on today's PCs. However, the total order of time in DE simulation is a bottleneck that severely limits the benefits of parallel simulation. This paper presents a new out-of-order simulator for multi-core parallel DE simulation of hardware/software designs at any abstraction Level. By localizing the simulation time and carefully handling events at different times, a System model can be simulated following a partial order of time. Subject to automatic static data analysis at compile time and table-based decisions at run time, threads can be issued early which reduces the idle time of available cores. Our experiments show high performance gains in simulation speed with only a small increase of compile time.

  • Parallel discrete event simulation of Transaction Level Models
    17th Asia and South Pacific Design Automation Conference, 2012
    Co-Authors: Rainer Domer, Weiwei Chen
    Abstract:

    Describing Multi-Processor Systems-on-Chip (MPSoC) at the abstract Electronic System Level (ESL) is one task, validating them efficiently is another. Here, fast and accurate System-Level simulation is critical. Recently, Parallel Discrete Event Simulation (PDES) has gained significant attraction again as it promises to utilize the existing parallelism in today's multicore CPU hosts. This paper discusses the parallel simulation of Transaction-Level Models (TLMs) described in System-Level Description Languages (SLDLs), such as SystemC and SpecC.We review how PDES exploits the explicit parallelism in the ESL design models and uses the parallel processing units available on multicore host PCs to significantly reduce the simulation time. We show experimental results for two highly parallel benchmarks as well as for two actual embedded applications.

Fei Xie - One of the best experts on this subject based on the ideXlab platform.

  • handling design and implementation optimizations in equivalence checking for behavioral synthesis
    Design Automation Conference, 2013
    Co-Authors: Zhenkun Yang, Kecheng Hao, Sandip Ray, Fei Xie
    Abstract:

    Behavioral synthesis involves generating hardware design via compilation of its Electronic System Level (ESL) description to an RTL implementation. Equivalence checking is critical to ensure that the synthesized RTL conforms to its ESL specification. Such equivalence checking must effectively handle design and implementation optimizations. We identify two key optimizations that complicate equivalence checking for behavioral synthesis: (1) operation gating, and (2) global variables. We develop a sequential equivalence checking (SEC) framework to compare ESL designs with RTL in the presence of these optimizations. Our approach can handle designs with more than 32K LoC RTL synthesized from practical ESL designs. Furthermore, our evaluation found a bug in a commercial tool, underlining both the importance of SEC and the effectiveness of our approach.

  • optimizing equivalence checking for behavioral synthesis
    Design Automation and Test in Europe, 2010
    Co-Authors: Kecheng Hao, Fei Xie, Sandip Ray, Jin Yang
    Abstract:

    Behavioral synthesis is the compilation of an Electronic System-Level (ESL) design into an RTL implementation. We present a suite of optimizations for equivalence checking of RTL generated through behavioral synthesis. The optimizations exploit the high-Level structure of the ESL description to ameliorate verification complexity. Experiments on representative benchmarks indicate that the optimizations can handle equivalence checking of synthesized designs with tens of thousands of lines of RTL.

Daniel Grosse - One of the best experts on this subject based on the ideXlab platform.

  • crave an advanced constrained random verification environment for Systemc
    International Symposium on System-on-Chip, 2012
    Co-Authors: Finn Haedicke, Daniel Grosse, Rolf Drechsler
    Abstract:

    A huge effort is necessary to design and verify complex Systems like System-on-Chip. Abstraction-based methodologies have been developed resulting in Electronic System Level (ESL) design. A prominent language for ESL design is SystemC offering different Levels of abstraction, interoperability and the creation of very fast models for early software development. For the verification of SystemC models, Constrained Random Verification (CRV) plays a major role. CRV allows to automatically generate simulation scenarios under the control of a set of constraints. Thereby, the generated stimuli are much more likely to hit corner cases. However, the existing SystemC Verification library (SCV), which provides CRV for SystemC models, has several deficiencies limiting the advantages of CRV. In this paper we present CRAVE, an advanced constrained random verification environment for SystemC. New dynamic features, enhanced usability and efficient constraint-solving reduce the user effort and thus improve the verification productivity.

  • tlm protocol compliance checking at the Electronic System Level
    Design and Diagnostics of Electronic Circuits and Systems, 2011
    Co-Authors: Mohamed Bawadekji, Daniel Grosse, Rolf Drechsler
    Abstract:

    Design and verification of embedded Systems at the Electronic System Level (ESL) is common practice. In particular, Transaction Level Modeling (TLM) is the major reason for the success of ESL design. However, when detailed protocols are modeled at lower Levels of TLM, the verification of the communication becomes a critical issue. In this paper, we present an approach for protocol compliance checking of new or detailed protocol implementations. They are checked against user-specified protocol sequences. We also analyze the protocol coverage achieved by the testbench and visualize the results on a protocol sequence graph. Experimental results for a SoC model demonstrate the advantages of our method.

  • proving transaction and System Level properties of untimed Systemc tlm designs
    Formal Methods, 2010
    Co-Authors: Daniel Grosse, Rolf Drechsler
    Abstract:

    Electronic System Level (ESL) design manages the enormous complexity of todays Systems by using abstract models. In this context Transaction Level Modeling (TLM) is state-of-the-art for describing complex communication without all the details. As ESL language, SystemC has become the de facto standard. Since the SystemC TLM models are used for early software development and as reference for hardware implementation their correct functional behavior is crucial. Admittedly, the best possible verification quality can be achieved with formal approaches. However, formal verification of TLM models is a hard task. Existing methods basically consider local properties or have extremely high run-time. In contrast, the approach proposed in this paper can verify “true” TLM properties, i.e. major TLM behavior like for instance the effect of a transaction and that the transaction is only started after a certain event can be proven. Our approach works as follows: After a fully automatic SystemC-to-C transformation, the TLM property is mapped to monitoring logic using C assertions and finite state machines. To detect a violation of the property the approach uses a BMC-based formulation over the outermost loop of the SystemC scheduler. In addition, we improve this verification method significantly by employing induction on the C model forming a complete and efficient approach. As shown by experiments state-of-the-art proof techniques allow proving important non-trivial behavior of SystemC TLM designs.