The Experts below are selected from a list of 309 Experts worldwide ranked by ideXlab platform
Hirofumi Akagi - One of the best experts on this subject based on the ideXlab platform.
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a high speed protection circuit for igbts subjected to hard switching faults
IEEE Transactions on Industry Applications, 2015Co-Authors: Takeshi Horiguchi, Shinichi Kinouchi, Yasushi Nakayama, Takeshi Oi, Hiroaki Urushibata, Shoji Okamoto, Shinji Tominaga, Hirofumi AkagiAbstract:This paper describes a high-speed protection circuit for insulated-Gate bipolar transistors (IGBTs) subjected to hard-switching faults (HSFs). The reverse transfer capacitance depends on the collector–emitter voltage, and it produces a significant effect on the switching behavior not only under normal conditions but also under HSF conditions. A Gate Charge characteristic under HSF conditions differs from that under normal turn-on conditions. Hence, an HSF can be detected by monitoring both the Gate–emitter voltage and the amount of Gate Charge during the turn-on transient period. IGBTs can be rapidly protected from destruction by using this method because a blanking time is unnecessary. Simulation and experiment verify the validity of the proposed high-speed protection circuit.
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A fast short-circuit protection method using Gate Charge characteristics of SiC MOSFETs
2015 IEEE Energy Conversion Congress and Exposition (ECCE), 2015Co-Authors: Takeshi Horiguchi, Shinichi Kinouchi, Yasushi Nakayama, Hirofumi AkagiAbstract:This paper describes a fast protection circuit for silicon carbide metal-oxide semiconductor field-effect transistors (SiC MOSFETs) subjected to hard-switching faults (HSFs). In terms of reliability of power converters, the protection of power semiconductors against short-circuit failures is of great concern. The reverse transfer capacitance increases with decreasing drain-source voltage during normal turn-on transient. Under HSF conditions, on the other hand, it hardly changes because the drain-source voltage remains high. As a consequence, quite a significant difference appears in Gate Charge characteristics between under HSF conditions and normal turn-on operation. Hence, an HSF can be detected by monitoring both the Gate- source voltage and the amount of Gate Charge. The proposed protection circuit has high noise tolerance because it monitors not only the Gate-source voltage but also the amount of Gate Charge. The validity of the protection circuit is verified by experiment. The proposed protection circuit can detect the HSF within only one microsecond.
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a high speed protection circuit for igbts subjected to hard switching faults
Applied Power Electronics Conference, 2014Co-Authors: Takeshi Horiguchi, Shinichi Kinouchi, Yasushi Nakayama, Takeshi Oi, Hiroaki Urushibata, Shoji Okamoto, Shinji Tominaga, Hirofumi AkagiAbstract:This paper describes a high-speed protection circuit for IGBTs subjected to hard-switching faults (HSF). The reverse transfer capacitance depends on a collector-emitter voltage and it produces a significant effect on a switching behavior not only under normal conditions but also under HSF conditions. A Gate Charge characteristic under HSF conditions differs from that under normal turn-on conditions. Hence, a hard-switching fault can be detected by monitoring both a Gate-emitter voltage and an amount of Gate Charge during the turn-on transient period. IGBTs can be rapidly protected from destruction because a blanking time is unnecessary. Simulation and experiment verify the validity of the proposed high-speed protection circuit.
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A short circuit protection method based on a Gate Charge characteristic
2014 International Power Electronics Conference (IPEC-Hiroshima 2014 - ECCE ASIA), 2014Co-Authors: Takeshi Horiguchi, Shinichi Kinouchi, Yasushi Nakayama, Hiroaki Urushibata, Shoji Okamoto, Shinji Tominaga, Hirofumi AkagiAbstract:This paper describes a high-speed circuit to protect IGBTs against short-circuit faults. The reverse transfer capacitance depends on a collector-emitter voltage and it produces a significant effect on a switching behavior under short-circuit fault conditions as well as under normal conditions. A Gate Charge characteristic under short-circuit fault conditions differs from that under normal turn-on conditions. Hence, hard-switching fault (HSF) can be detected by monitoring both a Gate-emitter voltage and an amount of Gate Charge. IGBTs can be rapidly protected from destruction because the protection circuit based on a Gate Charge characteristic does not require any blanking time. Fault under load can be also detected by almost the same circuit configuration. Simulation and experiment verify the validity of the novel protection circuit based on a Gate Charge characteristic.
Ichiro Omura - One of the best experts on this subject based on the ideXlab platform.
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ultra high speed short circuit protection for igbt with Gate Charge sensing
International Symposium on Power Semiconductor Devices and IC's, 2010Co-Authors: Kazufumi Yuasa, Soh Nakamichi, Ichiro OmuraAbstract:Short circuit (SC) protection for IGBT has been crucial issue since IGBTs have become major switching devices for power electronics applications. According to the IGBT performance improvement, chip current density has been increased and the chip has become as thin as 100µm. The high current density and thin wafer chip result in high temperature rising speed during SC condition and hence high speed protection scheme for IGBT is highly required. Conventional methods, such as sense IGBT configuration, have the response time of 5 micro second, for example, which is not sufficient to protect advanced IGBTs. In this paper, we propose a novel protection method with response time shorter than 1 micro second.
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suppression of dynamic on resistance increase and Gate Charge measurements in high voltage gan hemts with optimized field plate structure
IEEE Transactions on Electron Devices, 2007Co-Authors: Wataru Saito, Ichiro Omura, T Nitta, Yorito Kakiuchi, Yasunobu Saito, K Tsuda, Marina YamaguchiAbstract:The dynamic on-resistance increase associated with the current collapse phenomena in high-voltage GaN high-electron-mobility transistors (HEMTs) has been suppressed by employing an optimized field-plate (FP) structure. The fabricated GaN-HEMTs of 600 V/4.7 A and 940 V/4.4 A for power-electronics applications employ a dual-FP structure consisting of a short-Gate FP underneath a long-source FP. The measured on-resistance shows minimal increase during high-voltage switching due to increased electric-field uniformity between the Gate and drain as a result of using the dual FP. The Gate-drain Charge Q gd for the fabricated devices has also been measured to provide a basis for discussion of the ability of high-speed switching operation. Although Q gd /A (A: active device area) was almost the same as that of the conventional Si-power MOSFETs, R on A was dramatically reduced to about a seventh of the reported 600-V Si-MOSFET value. Therefore, R on Q gd for 600-V device was reduced to 0.32 OmeganC, which was approximately a sixth of that for the Si-power MOSFETs. The high-voltage GaN-HEMTs have significant advantages over silicon-power MOSFETs in terms of both the reduced on-resistance and the high-speed switching capability.
Takeshi Horiguchi - One of the best experts on this subject based on the ideXlab platform.
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a high speed protection circuit for igbts subjected to hard switching faults
IEEE Transactions on Industry Applications, 2015Co-Authors: Takeshi Horiguchi, Shinichi Kinouchi, Yasushi Nakayama, Takeshi Oi, Hiroaki Urushibata, Shoji Okamoto, Shinji Tominaga, Hirofumi AkagiAbstract:This paper describes a high-speed protection circuit for insulated-Gate bipolar transistors (IGBTs) subjected to hard-switching faults (HSFs). The reverse transfer capacitance depends on the collector–emitter voltage, and it produces a significant effect on the switching behavior not only under normal conditions but also under HSF conditions. A Gate Charge characteristic under HSF conditions differs from that under normal turn-on conditions. Hence, an HSF can be detected by monitoring both the Gate–emitter voltage and the amount of Gate Charge during the turn-on transient period. IGBTs can be rapidly protected from destruction by using this method because a blanking time is unnecessary. Simulation and experiment verify the validity of the proposed high-speed protection circuit.
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A fast short-circuit protection method using Gate Charge characteristics of SiC MOSFETs
2015 IEEE Energy Conversion Congress and Exposition (ECCE), 2015Co-Authors: Takeshi Horiguchi, Shinichi Kinouchi, Yasushi Nakayama, Hirofumi AkagiAbstract:This paper describes a fast protection circuit for silicon carbide metal-oxide semiconductor field-effect transistors (SiC MOSFETs) subjected to hard-switching faults (HSFs). In terms of reliability of power converters, the protection of power semiconductors against short-circuit failures is of great concern. The reverse transfer capacitance increases with decreasing drain-source voltage during normal turn-on transient. Under HSF conditions, on the other hand, it hardly changes because the drain-source voltage remains high. As a consequence, quite a significant difference appears in Gate Charge characteristics between under HSF conditions and normal turn-on operation. Hence, an HSF can be detected by monitoring both the Gate- source voltage and the amount of Gate Charge. The proposed protection circuit has high noise tolerance because it monitors not only the Gate-source voltage but also the amount of Gate Charge. The validity of the protection circuit is verified by experiment. The proposed protection circuit can detect the HSF within only one microsecond.
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a high speed protection circuit for igbts subjected to hard switching faults
Applied Power Electronics Conference, 2014Co-Authors: Takeshi Horiguchi, Shinichi Kinouchi, Yasushi Nakayama, Takeshi Oi, Hiroaki Urushibata, Shoji Okamoto, Shinji Tominaga, Hirofumi AkagiAbstract:This paper describes a high-speed protection circuit for IGBTs subjected to hard-switching faults (HSF). The reverse transfer capacitance depends on a collector-emitter voltage and it produces a significant effect on a switching behavior not only under normal conditions but also under HSF conditions. A Gate Charge characteristic under HSF conditions differs from that under normal turn-on conditions. Hence, a hard-switching fault can be detected by monitoring both a Gate-emitter voltage and an amount of Gate Charge during the turn-on transient period. IGBTs can be rapidly protected from destruction because a blanking time is unnecessary. Simulation and experiment verify the validity of the proposed high-speed protection circuit.
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A short circuit protection method based on a Gate Charge characteristic
2014 International Power Electronics Conference (IPEC-Hiroshima 2014 - ECCE ASIA), 2014Co-Authors: Takeshi Horiguchi, Shinichi Kinouchi, Yasushi Nakayama, Hiroaki Urushibata, Shoji Okamoto, Shinji Tominaga, Hirofumi AkagiAbstract:This paper describes a high-speed circuit to protect IGBTs against short-circuit faults. The reverse transfer capacitance depends on a collector-emitter voltage and it produces a significant effect on a switching behavior under short-circuit fault conditions as well as under normal conditions. A Gate Charge characteristic under short-circuit fault conditions differs from that under normal turn-on conditions. Hence, hard-switching fault (HSF) can be detected by monitoring both a Gate-emitter voltage and an amount of Gate Charge. IGBTs can be rapidly protected from destruction because the protection circuit based on a Gate Charge characteristic does not require any blanking time. Fault under load can be also detected by almost the same circuit configuration. Simulation and experiment verify the validity of the novel protection circuit based on a Gate Charge characteristic.
Bo Zhang - One of the best experts on this subject based on the ideXlab platform.
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Low Loss and Low EMI Noise CSTBT With Split Gate and Recessed Emitter Trench
'Institute of Electrical and Electronics Engineers (IEEE)', 2021Co-Authors: Jinping Zhang, Xiang Xiao, Rongrong Zhu, Qian Zhao, Bo ZhangAbstract:A novel carrier stored trench bipolar transistor (CSTBT) with split Gate (SG) and recessed emitter trench (SGRET CSTBT) is proposed. The proposed device features a SG structure with thicker oxide layer under the trench Gate and recessed trench emitter, respectively. Compared with the conventional CSTBT with recessed emitter trench (RET CSTBT), the proposed device not only significantly reduces the Gate-collector capacitance ( ${C} _{\mathrm{ GC}}$ ) but also alleviates the negative impact of the heavily doped n-type carrier stored layer on the breakdown voltage (BV). Simulation results show that with the similar BV of about 650V, the on-state voltage drop ( ${V} _{\mathrm{ ceon}}$ ) at ${J} _{\mathrm{ ce}}$ =200A/cm2 for the proposed SGRET CSTBT is only 1.11V, which is 0.19V lower than that of the conventional RET CSTBT. Moreover, compared with the conventional RET CSTBT, the ${C} _{\mathrm{ GC}}$ at the ${V} _{\mathrm{ ce}}$ of 25V, total Gate Charge ( ${Q} _{\mathrm{ G}}$ ) and miller plateau Charge ( ${Q} _{\mathrm{ GC}}$ ) for the proposed device are reduced by 84.3%, 38.6% and 51.6%, respectively. As a result, the trade-off relationship between the ${V} _{\mathrm{ ceon}}$ and turn-off loss ( ${E} _{\mathrm{ off}}$ ) as well as trade-off relationship between the turn-on loss ( ${E} _{\mathrm{ on}}$ ) and $\text{d}{V} _{\mathrm{ ak}} / \text{d}{t}$ of the free-wheeling diode (FWD) are significantly improved for the proposed device. At the same ${V} _{\mathrm{ ceon}}$ of 1.16V, the ${E} _{\mathrm{ off}}$ is reduced from 9.2mJ/cm2 of the conventional one to 3.3mJ/cm2 of the proposed device. At the same ${E} _{\mathrm{ on}}$ of 8.3mJ/cm2, the $\text{d}{V} _{\mathrm{ ak}} / \text{d}{t}$ of FWD for the proposed device is reduced by 24.5% compared with that of the conventional RET CSTBT, which significantly suppresses the EMI noise
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a split Gate vertical gan power transistor with intrinsic reverse conduction capability and low Gate Charge
International Symposium on Power Semiconductor Devices and IC's, 2018Co-Authors: Ruopu Zhu, Hong Tao, Qi Zhou, Yi Yang, Dong Wei, Liyang Zhu, Yu Shi, Wanjun Chen, Xiaorong Luo, Bo ZhangAbstract:In this work, a vertical normally-off GaN device featuring split-Gate with intrinsic reverse conduction (RCVFET) functionality and low Gate capacitance is proposed and studied by simulation. Different from the lateral AlGaN/GaN HEMT, the RC characteristics of the proposed RCVFET are independent with the threshold voltage of the device, while a low V R, ON of 0.8 V is obtained. Owing to the split-Gate design, the Gate Charge is respectably reduced that is beneficial for improving the switching speed of the RCVFET. The device exhibits a low Ron of 0.93 mΩ.cm2 and a BV of 1280V. The reverse recovery time is 13ns. The Q GD is 80 nC that is only one fifth of that obtained in the reference device without split-Gate.
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sic trench mosfet with integrated self assembled three level protection schottky barrier diode
IEEE Transactions on Electron Devices, 2018Co-Authors: Xing Tong, Alex Q Huang, Hong Tao, Kun Zhou, Yifan Jiang, Junning Jiang, Xiaochuan Deng, Xu She, Bo Zhang, Yourun ZhangAbstract:A silicon carbide (SiC) trench MOSFET (TMOS) with integrated three-level protection (TLP) Schottky barrier diode (SBD), named ITS-TMOS, is proposed and investiGated by simulation. The device features the integrated TLP-SBD that remarkably improves body diode characteristics while guarantees excellent fundamental performance of TMOS. In the blocking state, the P-base region, the trench Gate, and the P+ shield at the trench bottom serve as the TLP of the Schottky contact. Each protection assists in depleting the drift region beneath Schottky contact. Benefiting from the self-assembled TLP, the leakage current of the integrated body diode of the ITS-TMOS is significantly reduced. Moreover, the reverse turn-on voltage ( ${V} _{ \mathrm{\scriptscriptstyle ON}}$ ) and the Gate Charge ( ${Q} _{g}$ ) of the ITS-TMOS are 65% and 18% lower than those of the conventional TMOS, respectively. The improved overall performances make the SiC ITS-TMOS a competitive candidate for high-efficiency and high power density applications.
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Gate sensed method of load current imbalance measuring for paralleling igbt devices
International Symposium on Power Semiconductor Devices and IC's, 2016Co-Authors: Xiao Zeng, Fashun Yang, Qian Chen, Min Ren, Jinping Zhang, Wei Gao, Bo ZhangAbstract:In order to realize load current imbalance measuring for paralleling IGBT devices, the authors propose a novel method for measuring the imbalances from IGBT Gate Charge. In the study, an analytical model between Gate Charge and on-state current has been worked out to find the current differences of IGBT among each paralleled sub-circuits. The results from simulation show that the analytical model is effective and on-state static collector current of IGBT can be mapped from Gate Charge. For dynamic current time delay, it is also can be detected from the Gate Charge.
Shinichi Kinouchi - One of the best experts on this subject based on the ideXlab platform.
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a high speed protection circuit for igbts subjected to hard switching faults
IEEE Transactions on Industry Applications, 2015Co-Authors: Takeshi Horiguchi, Shinichi Kinouchi, Yasushi Nakayama, Takeshi Oi, Hiroaki Urushibata, Shoji Okamoto, Shinji Tominaga, Hirofumi AkagiAbstract:This paper describes a high-speed protection circuit for insulated-Gate bipolar transistors (IGBTs) subjected to hard-switching faults (HSFs). The reverse transfer capacitance depends on the collector–emitter voltage, and it produces a significant effect on the switching behavior not only under normal conditions but also under HSF conditions. A Gate Charge characteristic under HSF conditions differs from that under normal turn-on conditions. Hence, an HSF can be detected by monitoring both the Gate–emitter voltage and the amount of Gate Charge during the turn-on transient period. IGBTs can be rapidly protected from destruction by using this method because a blanking time is unnecessary. Simulation and experiment verify the validity of the proposed high-speed protection circuit.
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A fast short-circuit protection method using Gate Charge characteristics of SiC MOSFETs
2015 IEEE Energy Conversion Congress and Exposition (ECCE), 2015Co-Authors: Takeshi Horiguchi, Shinichi Kinouchi, Yasushi Nakayama, Hirofumi AkagiAbstract:This paper describes a fast protection circuit for silicon carbide metal-oxide semiconductor field-effect transistors (SiC MOSFETs) subjected to hard-switching faults (HSFs). In terms of reliability of power converters, the protection of power semiconductors against short-circuit failures is of great concern. The reverse transfer capacitance increases with decreasing drain-source voltage during normal turn-on transient. Under HSF conditions, on the other hand, it hardly changes because the drain-source voltage remains high. As a consequence, quite a significant difference appears in Gate Charge characteristics between under HSF conditions and normal turn-on operation. Hence, an HSF can be detected by monitoring both the Gate- source voltage and the amount of Gate Charge. The proposed protection circuit has high noise tolerance because it monitors not only the Gate-source voltage but also the amount of Gate Charge. The validity of the protection circuit is verified by experiment. The proposed protection circuit can detect the HSF within only one microsecond.
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a high speed protection circuit for igbts subjected to hard switching faults
Applied Power Electronics Conference, 2014Co-Authors: Takeshi Horiguchi, Shinichi Kinouchi, Yasushi Nakayama, Takeshi Oi, Hiroaki Urushibata, Shoji Okamoto, Shinji Tominaga, Hirofumi AkagiAbstract:This paper describes a high-speed protection circuit for IGBTs subjected to hard-switching faults (HSF). The reverse transfer capacitance depends on a collector-emitter voltage and it produces a significant effect on a switching behavior not only under normal conditions but also under HSF conditions. A Gate Charge characteristic under HSF conditions differs from that under normal turn-on conditions. Hence, a hard-switching fault can be detected by monitoring both a Gate-emitter voltage and an amount of Gate Charge during the turn-on transient period. IGBTs can be rapidly protected from destruction because a blanking time is unnecessary. Simulation and experiment verify the validity of the proposed high-speed protection circuit.
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A short circuit protection method based on a Gate Charge characteristic
2014 International Power Electronics Conference (IPEC-Hiroshima 2014 - ECCE ASIA), 2014Co-Authors: Takeshi Horiguchi, Shinichi Kinouchi, Yasushi Nakayama, Hiroaki Urushibata, Shoji Okamoto, Shinji Tominaga, Hirofumi AkagiAbstract:This paper describes a high-speed circuit to protect IGBTs against short-circuit faults. The reverse transfer capacitance depends on a collector-emitter voltage and it produces a significant effect on a switching behavior under short-circuit fault conditions as well as under normal conditions. A Gate Charge characteristic under short-circuit fault conditions differs from that under normal turn-on conditions. Hence, hard-switching fault (HSF) can be detected by monitoring both a Gate-emitter voltage and an amount of Gate Charge. IGBTs can be rapidly protected from destruction because the protection circuit based on a Gate Charge characteristic does not require any blanking time. Fault under load can be also detected by almost the same circuit configuration. Simulation and experiment verify the validity of the novel protection circuit based on a Gate Charge characteristic.