The Experts below are selected from a list of 38106 Experts worldwide ranked by ideXlab platform
Chan Eon Park - One of the best experts on this subject based on the ideXlab platform.
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solution processed flexible zno transparent thin film transistors with a polymer Gate Dielectric fabricated by microwave heating
Nanotechnology, 2009Co-Authors: Chanwoo Yang, Kipyo Hong, Jaeyoung Jang, Dae Sung Chung, Tae Kyu An, Woonseop Choi, Chan Eon ParkAbstract:We report the development of solution-processed zinc oxide (ZnO) transparent thin-film transistors (TFTs) with a poly(2-hydroxyethyl methacrylate) (PHEMA) Gate Dielectric on a plastic substrate. The ZnO nanorod film active layer, prepared by microwave heating, showed a highly uniform and densely packed array of large crystal size (58 nm) in the [002] direction of ZnO nanorods on the plasma-treated PHEMA. The flexible ZnO TFTs with the plasma-treated PHEMA Gate Dielectric exhibited an electron mobility of 1.1 cm2 V−1 s−1, which was higher by a factor of ~8.5 than that of ZnO TFTs based on the bare PHEMA Gate Dielectric.
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effects of polar functional groups and roughness topography of polymer Gate Dielectric layers on pentacene field effect transistors
Organic Electronics, 2007Co-Authors: Kwonwoo Shin, Sang Yoon Yang, Chanwoo Yang, Hayoung Jeon, Chan Eon ParkAbstract:Abstract The present study analyzed the effects of the polar functional groups and rough topography of the Gate Dielectric layer on the characteristics of pentacene field-effect transistors. For this purpose, prior to deposition of the organic semiconductor, we introduced polar functional groups and created a rough topography onto the poly(methylmethacrylate)/Al2O3 Gate Dielectric layer using oxygen plasma treatment, and controlled the number of polar groups using an aging process. The mobility decrease observed after oxygen plasma treatment ranged from 0.2 to
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the effect of Gate Dielectric surface energy on pentacene morphology and organic field effect transistor characteristics
Advanced Functional Materials, 2005Co-Authors: Sang Yoon Yang, Kwonwoo Shin, Chan Eon ParkAbstract:The effects of the surface energy of polymer Gate Dielectrics on pentacene morphology and the electrical properties of pentacene field-effect transistors (FETs) are reported, using surface-energy-controllable poly(imide-siloxane)s as Gate-Dielectric layers. The surface energy of Gate Dielectrics strongly influences the pentacene film morphology and growth mode, producing Stranski–Krastanov growth with large and dendritic grains at high surface energy and three-dimensional island growth with small grains at low surface energy. In spite of the small grain size (≈ 300 nm) and decreased ordering of pentacene molecules vertical to the Gate Dielectric with low surface energy, the mobility of FETs with a low-surface-energy Gate Dielectric is larger by a factor of about five, compared to their high-surface-energy counterparts. In pentacene growth on the low-surface-energy Gate Dielectric, interconnection between grains is observed and gradual lateral growth of grains causes the vacant space between grains to be filled. Hence, the higher mobility of the FETs with low-surface-energy Gate Dielectrics can be achieved by interconnection and tight packing between pentacene grains. On the other hand, the high-surface-energy Dielectric forms the first pentacene layer with some voids and then successive, incomplete layers over the first, which can limit the transport of charge carriers and cause lower carrier mobility, in spite of the formation of large grains (≈ 1.3 μm) in a thicker pentacene film.
Hagen Klauk - One of the best experts on this subject based on the ideXlab platform.
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high performance zno nanowire transistors with aluminum top Gate electrodes and naturally formed hybrid self assembled monolayer alox Gate Dielectric
ACS Nano, 2014Co-Authors: Daniel Kalblein, Hyeyeon Ryu, Frederik Ante, Bernhard Fenk, Kersten Hahn, Klaus Kern, Hagen KlaukAbstract:A method for the formation of a low-temperature hybrid Gate Dielectric for high-performance, top-Gate ZnO nanowire transistors is reported. The hybrid Gate Dielectric consists of a self-assembled monolayer (SAM) and an aluminum oxide layer. The thin aluminum oxide layer forms naturally and spontaneously when the aluminum Gate electrode is deposited by thermal evaporation onto the SAM-covered ZnO nanowire, and its formation is facilitated by the poor surface wetting of the aluminum on the hydrophobic SAM. The hybrid Gate Dielectric shows excellent electrical insulation and can sustain voltages up to 6 V. ZnO nanowire transistors utilizing the hybrid Gate Dielectric feature a large transconductance of 50 μS and large on-state currents of up to 200 μA at Gate-source voltages of 3 V. The large on-state current is sufficient to drive organic light-emitting diodes with an active area of 6.7 mm2 to a brightness of 445 cd/m2. Inverters based on ZnO nanowire transistors and thin-film carbon load resistors operate ...
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Low-voltage organic transistors with an amorphous molecular Gate Dielectric
Nature, 2004Co-Authors: Marcus Halik, Steffen Malsch, Christine Dehm, Markus Brunnbauer, Markus Schütz, Franz Effenberger, Gunter Schmid, Ute Zschieschang, Hagen Klauk, Francesco StellacciAbstract:Organic thin film transistors (TFTs) are of interest for a variety of large-area electronic applications, such as displays, sensors and electronic barcodes. One of the key problems with existing organic TFTs is their large operating voltage, which often exceeds 20 V. This is due to poor capacitive coupling through relatively thick Gate Dielectric layers: these Dielectrics are usually either inorganic oxides or nitrides, or insulating polymers, and are often thicker than 100 nm to minimize Gate leakage currents. Here we demonstrate a manufacturing process for TFTs with a 2.5-nm-thick molecular self-assembled monolayer (SAM) Gate Dielectric and a high-mobility organic semiconductor (pentacene). These TFTs operate with supply voltages of less than 2 V, yet have Gate currents that are lower than those of advanced silicon field-effect transistors with SiO2 Dielectrics. These results should therefore increase the prospects of using organic TFTs in low-power applications (such as portable devices). Moreover, molecular SAMs may even be of interest for advanced silicon transistors where the continued reduction in Dielectric thickness leads to ever greater Gate leakage and power dissipation.
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high mobility polymer Gate Dielectric pentacene thin film transistors
Journal of Applied Physics, 2002Co-Authors: Hagen Klauk, Marcus Halik, Gunter Schmid, Ute Zschieschang, Wolfgang Radlik, Werner WeberAbstract:We have fabricated pentacene organic thin film transistors with spin-coated polymer Gate Dielectric layers, including cross-linked polyvinylphenol and a polyvinylphenol-based copolymer, and obtained devices with excellent electrical characteristics, including carrier mobility as large as 3 cm2/V s, subthreshold swing as low as 1.2 V/decade, and on/off current ratio of 105. For comparison, we have also fabricated pentacene transistors using thermally grown silicon dioxide as the Gate Dielectric and obtained carrier mobilities as large as 1 cm2/V s and subthreshold swing as low as 0.5 V/decade.
Woo Young Choi - One of the best experts on this subject based on the ideXlab platform.
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hetero Gate Dielectric tunneling field effect transistors
IEEE Transactions on Electron Devices, 2010Co-Authors: Woo Young ChoiAbstract:A tunneling field-effect transistor (TFET) is considered one of the most promising alternatives to a metal-oxide-semiconductor field-effect transistor due to its immunity to short-channel effects. However, TFETs have suffered from low on-current, severe ambipolar behavior, and gradual transition between on- and off -states. To address those issues, the authors have proposed hetero-Gate-Dielectric TFETs. The proposed device enhances on-current, suppresses ambipolar behavior, and makes abrupt on-off transition by replacing the source-side Gate insulator with a high-k material, which induces a local minimum of the conduction band edge at the tunneling junction.
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hetero Gate Dielectric tunneling field effect transistors
IEEE Transactions on Electron Devices, 2010Co-Authors: Woo Young Choi, Woojun LeeAbstract:A tunneling field-effect transistor (TFET) is considered one of the most promising alternatives to a metal-oxide-semiconductor field-effect transistor due to its immunity to short-channel effects. However, TFETs have suffered from low on-current, severe ambipolar behavior, and gradual transition between on- and off -states. To address those issues, the authors have proposed hetero-Gate-Dielectric TFETs. The proposed device enhances on-current, suppresses ambipolar behavior, and makes abrupt on-off transition by replacing the source-side Gate insulator with a high-k material, which induces a local minimum of the conduction band edge at the tunneling junction.
P.t. Lai - One of the best experts on this subject based on the ideXlab platform.
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gaas metal oxide semiconductor capacitor with nd based high k oxynitrides as Gate Dielectric and passivation layer
IEEE Transactions on Electron Devices, 2018Co-Authors: L N Liu, H W Choi, W M Tang, P.t. LaiAbstract:GaAs metal–oxide–semiconductor capacitors with NdTaON as Gate Dielectric and NdAlON, NdON or AlON as interfacial passivation layer (IPL) are fabricated, and their interfacial and electrical properties are compared with their counterpart without IPL. Experimental results show that owing to the suppressed hygroscopicity of NdON by Al incorporation, best improvements in electrical properties and reliability are achieved for the sample with NdAlON IPL (low interface-state density ( $8 \times 10^{11}$ cm−2/eV), small flatband voltage (0.72 V), negligible hysteresis (43 mV), small frequency dispersion, and low Gate leakage current density ( $2.56 \times 10^{-6}$ A/cm2 at Vfb + 1 V). These should be attributed to suppressed growth of unstable Ga and As oxides on the GaAs surface and reduced in-diffusion of elements from the Gate Dielectric to the GaAs surface by the NdAlON IPL during Gate-Dielectric annealing.
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A carrier-mobility model for high-k Gate-Dielectric Ge MOSFETs with metal Gate electrode
Microelectronics Reliability, 2010Co-Authors: X. Xiao, P.t. LaiAbstract:A mobility model for high-k Gate-Dielectric Ge pMOSFET with metal Gate electrode is proposed by considering the scattering of channel carriers by surface-optical phonons in the high-k Gate Dielectric. The effects of structural and physical parameters (e.g. Gate Dielectric thickness, electron density, effective electron mass and permittivity of Gate electrode) on the carrier mobility are investiGated. The carrier mobility of Ge pMOSFET with metal Gate electrode is compared to that with poly-Si Gate electrode. It is theoretically shown that the carrier mobility can be largely enhanced when poly-Si Gate electrode is replaced by metal Gate electrode. This is because metal Gate electrode plays a significant role in screening the coupling between the optical phonons in the high-k Gate Dielectric and the charge carriers in the conduction channel.
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A fringing-capacitance model for deep-submicron MOSFET with high-k Gate Dielectric
Microelectronics Reliability, 2008Co-Authors: P.t. Lai, Jianguo GuanAbstract:An analytical model of fringing capacitances for deep-submicron MOSFET with high-k Gate Dielectric, including Gate Dielectric fringing-capacitance and Gate electrode fringing-capacitance, is obtained by the conformal-mapping transformation method. It is demonstrated that the fringing-capacitance effect is enhanced as the thickness of Gate electrode or the Dielectric constant of either Gate Dielectric or sidewall spacer increases. Moreover, the influence of fringing-capacitance on threshold voltage is demonstrated.
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Improved carrier mobility for pentacene TFT by NH3 annealing of Gate Dielectric
Solid-State Electronics, 2007Co-Authors: M.c. Kwan, P.t. Lai, K.h. Cheng, Chi-ming CheAbstract:Abstract The carrier mobility of pentacene OTFT is enhanced by annealing its Gate Dielectric (SiO 2 ) in NH 3 . The device has a field-effect mobility of 0.53 cm 2 /V s, with on/off current ratio of 10 6 , and subthreshold slope of 2.4 V per decade. When compared with the control sample with N 2 -annealed SiO 2 as Gate Dielectric, the mobility of the proposed pentacene OTFT is increased by over 50%. AFM micrographs show that the higher mobility should be due to the smoother Gate-Dielectric surface passivated by the NH 3 annealing, and also larger pentacene grains grown on the smoother Gate-Dielectric surface.
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2D Threshold-Voltage Model for High-k Gate-Dielectric MOSFETs
2006Co-Authors: P.t. Lai, Wei J. ChenAbstract:New boundary conditions and a 2D potential distribution along the channel of a high-k Gate-Dielectric MOSFET,including both the Gate Dielectric material region and the depletion region,are given.Based on this distribution,a 2D threshold-voltage model with the fringing-field and short-channel effects is developed for a high-k Gate-Dielectric MOSFET.The model agrees well with experimental data and a quasi 2D model,and is even more accurate than the quasi 2D model at higher drain voltages.Factors affecting the threshold behavior of the high-k Gate-Dielectric MOSFET are discussed in detail.
Kevin J Chen - One of the best experts on this subject based on the ideXlab platform.
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characterization of leakage and reliability of sin x Gate Dielectric by low pressure chemical vapor deposition for gan based mis hemts
IEEE Transactions on Electron Devices, 2015Co-Authors: Mengyuan Hua, Cheng Liu, Shu Yang, Shenghou Liu, Zhihua Dong, Yong Cai, Baoshun Zhang, Kevin J ChenAbstract:In this paper, we systematically investiGated the leakage and breakdown mechanisms of the low-pressure chemical vapor deposition (LPCVD) silicon nitride thin film deposited on AlGaN/GaN heterostructures. The LPCVD-SiN x Gate Dielectric exhibits low leakage and high breakdown electric field. The dominant mechanism of the leakage current through LPCVD-SiN x Gate Dielectric is identified to be Poole–Frenkel emission at low electric field and Fowler–Nordheim tunneling at high electric field. Both electric-field-accelerated and temperature-accelerated time-dependent Dielectric breakdown of the LPCVD-SiN x Gate Dielectric were also investiGated.
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gan based metal insulator semiconductor high electron mobility transistors using low pressure chemical vapor deposition sin x as Gate Dielectric
IEEE Electron Device Letters, 2015Co-Authors: Mengyuan Hua, Cheng Liu, Shu Yang, Shenghou Liu, Zhihua Dong, Yong Cai, Baoshun Zhang, Kevin J ChenAbstract:In this letter, silicon nitride (SiN x ) film deposited at 780 °C by low-pressure chemical vapor deposition (LPCVD) was employed as Gate Dielectric for GaN-based metal–insulator–semiconductor high-electron-mobility transistors. The LPCVD-SiN x exhibit improved Gate Dielectric performance than the plasma enhanced chemical vapor deposition-SiN x , including smaller forward and reverse Gate leakage, and higher forward Gate breakdown voltage.
