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Dim-lee Kwong - One of the best experts on this subject based on the ideXlab platform.
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Ultrathin HfO 2 "EOT 0.75 nm… Gate Stack with TaN/HfN Electrodes Fabricated Using a High-Temperature Process
Electrochemical and Solid-State Letters, 2005Co-Authors: Jian Kang, C. Ren, Daniel S. H. Chan, Xuenan Liu, Dim-lee KwongAbstract:With the continuous scaling of the complementary metal oxide semiconductor CMOS technology, high-k Gate dielectrics will be needed to replace conventional SiO2 Gate dielectrics for addressing the excessive high leakage concern. 1 HfO2 has been considered as one of the most promising candidates for such applications. 2 Much effort has been made in developing a HfO2 Gate Stack with equivalent oxide thickness EOT of less than 1 nm. 3-7 Although the asdeposited HfO2-based Gate dielectrics with metal Gate electrode could achieve an EOT 1 nm, a significant increase of both the EOT and the leakage current have been reported after the Gate Stack has been subjected to high temperature postmetallization annealing PMA. 3-6 The increase of EOT during PMA has been speculated to be caused by either the reaction at the metal Gate/HfO2 interface and/or the poor oxygen diffusion barrier of the metal Gate electrode. This thermal instability is a major concern for conventional Gatefirst CMOS processing. In this article, we have demonstrated a high-quality HfO2 Gate Stack fabricated using NH3-based surface nitridation prior to HfO2 deposition in order to suppress interfacial oxidation at the HfO2/Si interface as well as the HfN Gate electrode that has been shown to be an excellent oxygen diffusion barrier.
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CMOS integration issues with high-k Gate Stack
Proceedings of the 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2004 (IEEE Cat. No.04TH8743), 1Co-Authors: Dim-lee KwongAbstract:Continual CMOS scaling requires the implementation of high-k Gate dielectrics with metal Gate to alleviate the rapid Gate tunneling current increase associated with aggressive EOT scaling. The purpose of this paper is to review some of the integration challenges that high-k/metal Gate Stack technology is facing. This includes thermal stability of high-k against crystallization, phase separation, and interfacial reaction with underlying Si, charges/traps in high-k as well as at interfaces, channel carrier mobility degradation, EOT control and scaling, work function control for dual-Gate CMOS integration, and Gate Stack reliability. The engineering of the high-k/Si as well as metal/high-k interfaces is identified as the most important factor for achieving EOT
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Time-dependent dielectric breakdown in poly-Si CVD HfO/sub 2/ Gate Stack
2002 IEEE International Reliability Physics Symposium. Proceedings. 40th Annual (Cat. No.02CH37320), 1Co-Authors: S J Lee, Choong-ho Lee, Chang Hwan Choi, Dim-lee KwongAbstract:In this paper, we present a comprehensive study on long-term reliability of CVD HfO/sub 2/ Gate Stacks with n/sup +/-poly-Si Gate electrodes. The area dependence and temperature acceleration (25-150/spl deg/C) of TDDB, defect generation rate, and critical defect density of CVD HfO/sub 2/ Gate Stacks are studied. Results show that 10 year lifetime of HfO/sub 2//n/sup +/-poly-Si Gate Stack (EOT = 14.5 /spl Aring/) is projected for Vg = -2.0 V @ 25/spl deg/C and Vg = -1.56 V @ 150/spl deg/C. This excellent reliability characteristics of HfO/sub 2/ Gate Stack is mainly attributed to the thicker physical thickness of HfO/sub 2/, resulting in significant reduction of tunneling leakage current by a factor of 10/sup 3//spl sim/10/sup 4/ while maintaining comparable Weibull slope factor. In addition, the critical defect density of HfO/sub 2/ Gate Stack is comparable to SiO/sub 2/ with similar physical thickness. However, considering the cumulative impact of temperature acceleration at 150/spl deg/C, scaling of an effective Gate oxide area of 0.1 cm/sup 2/ and a maximum allowed fraction of failures of 0.01%, the maximum allowed operating voltage is projected to be only /spl sim/0.85 V for HfO/sub 2//poly-Si Gate Stack with EOT = 14.5 /spl Aring/.
Akira Toriumi - One of the best experts on this subject based on the ideXlab platform.
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new insight into mos Gate Stack formations on ge and sige from thermodynamics reaction kinetics and nanoscale engineering
International Electron Devices Meeting, 2019Co-Authors: Akira Toriumi, Tomonori NishimuraAbstract:Oxidation and thermal robustness of Gate Stacks in Ge and SiGe are intensively investiGated. The key points of new understanding in this work are twofold. One is that GeO 2 /Ge interface reaction occurs inhomogeneously, resulting in agglomerated Ge region formation. The other is that Si in SiGe is oxidized by GeO 2 and Ge agglomeration also occurs on SiGe surface. Scientific tips are proposed for wellcontrolled Ge and SiGe Gate Stack formation.
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Impact of Gate Stack Design on Improving Subthreshold Swing Behaviors in Ferroelectric-Gate Field-Effect Transistors
2019 International Symposium on VLSI Technology Systems and Application (VLSI-TSA), 2019Co-Authors: Shinji Migita, Hiroyuki Ota, Akira Toriumi, Takashi MatsukawaAbstract:Ferroelectric-Gate field-effect transistor (FE-FET) is an attractive device for both memory and logic applications. The metal-ferroelectric-metal-insulator-semiconductor (MFMIS) Gate Stack structure is useful to solve the issue of charge unbalance between ferroelectric and metal-insulator-semiconductor (MIS) capacitors in FE-FETs. In this study, the function of the MFMIS Gate Stack for the improvement of subthreshold behaviors in FE-FETs is analyzed. The results indicate that the design of capacitor-area-ratio in an MFMIS structure enhances the ferroelectric poling component relative to the paraelectric component and increases the charge boost efficiency, thereby leading to improved subthreshold swing.
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Yttrium scandate thin film as alternative high-permittivity dielectric for germanium Gate Stack formation
Applied Physics Letters, 2015Co-Authors: Choong Hyun Lee, Tomonori Nishimura, Akira ToriumiAbstract:We investiGated yttrium scandate (YScO3) as an alternative high-permittivity (k) dielectric thin film for Ge Gate Stack formation. Significant enhancement of k-value is reported in YScO3 comparing to both of its binary compounds, Y2O3 and Sc2O3, without any cost of interface properties. It suggests a feasible approach to a design of promising high-k dielectrics for Ge Gate Stack, namely, the formation of high-k ternary oxide out of two medium-k binary oxides. Aggressive scaling of equivalent oxide thickness (EOT) with promising interface properties is presented by using YScO3 as high-k dielectric and yttrium-doped GeO2 (Y-GeO2) as interfacial layer, for a demonstration of high-k Gate Stack on Ge. In addition, we demonstrate Ge n-MOSFET performance showing the peak electron mobility over 1000 cm2/V s in sub-nm EOT region by YScO3/Y-GeO2/Ge Gate Stack.
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structural and thermodynamic consideration of metal oxide doped geo2 for Gate Stack formation on germanium
Journal of Applied Physics, 2014Co-Authors: Choong Hyun Lee, Tomonori Nishimura, Wenfeng Zhang, Kosuke Nagashio, Akira ToriumiAbstract:A systematic investigation was carried out on the material and electrical properties of metal oxide doped germanium dioxide (M-GeO2) on Ge. We propose two criteria on the selection of desirable M-GeO2 for Gate Stack formation on Ge. First, metal oxides with larger cation radii show stronger ability in modifying GeO2 network, benefiting the thermal stability and water resistance in M-GeO2/Ge Stacks. Second, metal oxides with a positive Gibbs free energy for germanidation are required for good interface properties of M-GeO2/Ge Stacks in terms of preventing the Ge-M metallic bond formation. Aggressive equivalent oxide thickness scaling to 0.5 nm is also demonstrated based on these understandings.
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enhancement of thermal stability and water resistance in yttrium doped geo2 ge Gate Stack
Applied Physics Letters, 2014Co-Authors: Choong Hyun Lee, Tomonori Nishimura, Wenfeng Zhang, Kosuke Nagashio, Akira ToriumiAbstract:We have systematically investiGated the material and electrical properties of yttrium-doped GeO2 (Y-GeO2) on Germanium (Ge). A significant improvement of both thermal stability and water resistance were demonstrated by Y-GeO2/Ge Stack, compared to that of pure GeO2/Ge Stack. The excellent electrical properties of Y-GeO2/Ge Stacks with low Dit were presented as well as enhancement of dielectric constant in Y-GeO2 layer, which is beneficial for further equivalent oxide thickness scaling of Ge Gate Stack. The improvement of thermal stability and water resistance are discussed both in terms of the Gibbs free energy lowering and network modification of Y-GeO2.
Miinjang Chen - One of the best experts on this subject based on the ideXlab platform.
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double nitridation of crystalline zro 2 al 2 o 3 buffer Gate Stack with high capacitance low leakage and improved thermal stability
Applied Surface Science, 2015Co-Authors: Jhih Jie Huang, Yi Jen Tsai, Meng Chen Tsai, Miinjang ChenAbstract:Abstract The Gate dielectric Stack composed of crystalline ZrO 2 and Al 2 O 3 buffer layer treated with double nitridation was developed to reduce the capacitance equivalent thickness (CET), leakage current density ( J g ), interfacial state density ( D it ), and enhance thermal stability as well. A high dielectric constant of the Gate Stack was provided by the crystalline ZrO 2 with tetragonal/cubic phase. The J g and D it were suppressed by the insertion of the Al 2 O 3 buffer layer treated with remote NH 3 plasma nitridation because of the deactivation of the oxygen vacancies and the well passivation of the Si dangling bonds. A further nitridation using remote N 2 plasma on ZrO 2 was carried out to reduce the CET and J g by the enhancement of the dielectric constant and the deactivation of the grain boundaries and oxygen vacancies. Accordingly, a low CET of 1.09 nm, J g of 3.43 × 10 −5 A/cm 2 , and D it of 3.35 × 10 11 cm −2 eV −1 were achieved in the crystalline ZrO 2 /Al 2 O 3 buffer Gate Stack treated with the double nitridation. The hysteresis was also minimized significantly by the post-deposition annealing at 800 °C, which is attributed to the enhanced thermal stability. The results indicate that the crystalline high- K dielectrics/buffer layer with double nitridation treatments is a promising Gate Stack structure beneficial to the sub-nanometer CET scaling in the future.
R.s. Gupta - One of the best experts on this subject based on the ideXlab platform.
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Assessment of analog RF performance for insulated shallow extension (ISE) cylindrical surrounding Gate (CSG) MOSFET incorporating Gate Stack
Microsystem Technologies, 2019Co-Authors: Nitin Trivedi, Mridula Gupta, Subhasis Haldar, Manoj Kumar, S. S. Deswal, R.s. GuptaAbstract:In this paper, insulated shallow extension cylindrical surrounding Gate (ISE-CSG) MOSFET with high-k Gate Stack has been proposed and extensively investiGated. The performance of high-k ISE-CSG MOSFET has been compared with cylindrical surrounding Gate MOSFET. ISE-CSG with high-k Gate Stack has number of desirable features at 30 nm regimes. The results reveal that ISE-CSG MOSFET with Gate Stack is more immune to short channel effects because of improved carrier transportation capability. It has been observed that high-k ISE-CSG MOSFET shows improved figure of merits as drive current (I_ON), I_ON/I_OFF ratio, transconductance (g_m), cutoff frequency f_T, transconductance generation factor, intrinsic gain (A_v), transconductance frequency product, gain transconductance frequency product and gain frequency product. ISE-CSG with high-k gives better control over the depletion region and therefore it is a suitable device for high speed, high frequency and analog/RF circuit applications.
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Modelling challenges in sub-100 nm Gate Stack MOSFETs
Semiconductor Science and Technology, 2006Co-Authors: Tina Mangla, Amit Sehgal, Mridula Gupta, R.s. GuptaAbstract:The aim of this work is to present a two-dimensional analysis for different Gate Stack dielectric structured n-MOSFETs with carrier quantization effects. The model is developed using Green's function for solving Poisson's equation, without implying the extensive effort required for a fully self-consistent solution of the Schrodinger and Poisson equations. Explicit results for potential distribution, threshold voltage and drain current, with different structural and bias parameters, have been presented, typical in the operation of modern devices. The model includes short channel, drain bias, and junction curvature effects. Based on extensive simulation and developed formulation, it is found that the conventional concept of a scaled transformation method for Gate Stack structures to replace silicon-dioxide (SiO2) dielectric thickness with a thicker high dielectric does not predict the same characteristics. It has also been shown that using double-layer Gate Stack structures with low-k dielectric as the spacer material can well confine the electric fields within the channel, thereby enhancing Gate controllability on the channel charge. Comparison of the results thus obtained is done with simulated results to justify the analysis.
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modeling and simulation of a nanoscale three region tri material Gate Stack trimgas mosfet for improved carrier transport efficiency and reduced hot electron effects
IEEE Transactions on Electron Devices, 2006Co-Authors: K Goel, Mridula Gupta, Manoj Saxena, R.s. GuptaAbstract:Two-dimensional (2-D) analytical modeling for a novel multiple region MOSFET device architecture-Tri-Material Gate Stack MOSFET-is presented, which shows reduced short-channel effects at short Gate lengths. Using a three-region analysis in the horizontal direction and a universal depletion width boundary condition, the 2-D potential and electric field distribution in the channel region along with the threshold voltage of the device are obtained. The proposed model is capable of modeling electrical characteristics like surface potential, electric field, and threshold voltage of various other existent MOSFET structures like dual-material-Gate, electrically induced shallow junction/straddle-Gate (side-Gate), and single-material-Gate MOSFETs, with and without the Gate Stack architecture. The 2-D device simulator ATLAS is used over a wide range of parameters and bias conditions to validate the analytical results
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Modeling and simulation of asymmetric Gate Stack (ASYMGAS)-MOSFET
Solid-State Electronics, 2003Co-Authors: Manoj Saxena, Mridula Gupta, Subhasis Haldar, R.s. GuptaAbstract:Abstract We propose a new structure, asymmetric Gate Stack (ASYMGAS)-MOSFET and its 2-D analytical model. There is two-layer Gate Stack oxide near the drain and single Gate oxide near the source. The model predicts a step function profile in the potential along the channel, which ensures reduced DIBL. In ASYMGAS-MOSFET, the average electric field in the channel is enhanced, and therefore electron velocity, near the source, which improves the overall carrier transport efficiency. The results so obtained are verified using a two-dimensional device simulator, ATLAS, over a wide range of device parameters and bias conditions. Good agreement is obtained for channel lengths down to 0.15 μm. Thus, confirming the validity of our model.
D L Kwong - One of the best experts on this subject based on the ideXlab platform.
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ultrathin hfo 2 eot 0 75 nm Gate Stack with tan hfn electrodes fabricated using a high temperature process
Electrochemical and Solid State Letters, 2005Co-Authors: J F Kang, D.s.h. Chan, H Y Yu, M F Li, D L KwongAbstract:With the continuous scaling of the complementary metal oxide semiconductor CMOS technology, high-k Gate dielectrics will be needed to replace conventional SiO2 Gate dielectrics for addressing the excessive high leakage concern. 1 HfO2 has been considered as one of the most promising candidates for such applications. 2 Much effort has been made in developing a HfO2 Gate Stack with equivalent oxide thickness EOT of less than 1 nm. 3-7 Although the asdeposited HfO2-based Gate dielectrics with metal Gate electrode could achieve an EOT 1 nm, a significant increase of both the EOT and the leakage current have been reported after the Gate Stack has been subjected to high temperature postmetallization annealing PMA. 3-6 The increase of EOT during PMA has been speculated to be caused by either the reaction at the metal Gate/HfO2 interface and/or the poor oxygen diffusion barrier of the metal Gate electrode. This thermal instability is a major concern for conventional Gatefirst CMOS processing. In this article, we have demonstrated a high-quality HfO2 Gate Stack fabricated using NH3-based surface nitridation prior to HfO2 deposition in order to suppress interfacial oxidation at the HfO2/Si interface as well as the HfN Gate electrode that has been shown to be an excellent oxygen diffusion barrier.
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high quality ultra thin cvd hfo sub 2 Gate Stack with poly si Gate electrode
International Electron Devices Meeting, 2000Co-Authors: S J Lee, H F Luan, W P Bai, C H Lee, T S Jeon, Y Senzaki, D Roberts, D L KwongAbstract:We have developed and demonstrated an in-situ rapid thermal CVD (RTCVD) process for the fabrication of high quality ultra thin CVD HfO/sub 2/ Gate Stack that is compatible with conventional self-aligned poly-Si Gate technology. These poly-Si Gated HfO/sub 2/ Gate Stack show excellent interface properties, EOT=10.4 /spl Aring/, and leakage current Jg=0.23 mA/cm/sup 2/ @Vg=-1 V which is several orders of magnitude lower than RTO SiO/sub 2/ with poly-Si Gate. In addition, the HfO/sub 2/ Gate Stack is thermally stable in direct contact with n/sup +/-poly Si Gate under typical dopant activation conditions. These films also show excellent reliability under high-field electrical stress. We have also fabricated and demonstrated NMOSFETs, and studied boron penetration in HfO/sub 2/ Gate Stack with p/sup +/-poly Si Gate.