The Experts below are selected from a list of 1830 Experts worldwide ranked by ideXlab platform
Rao Tummala - One of the best experts on this subject based on the ideXlab platform.
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design and demonstration of a 2 5 d glass Interposer bga package for high bandwidth and low cost
IEEE Transactions on Components Packaging and Manufacturing Technology, 2017Co-Authors: Brett Sawyer, Vanessa Smet, Venky Sundaram, Yuya Suzuki, Ryuta Furuya, Chandrasekharan Nair, Tingchia Huang, Kadappan Panayappan, Rao TummalaAbstract:Consumer demand for mobile services is expected to grow with the continued proliferation of connected devices including smartphones, wearables, and Internet of things. As a result, high-performance computing systems that support the core network and cloud infrastructures for these connected devices require unprecedented die-to-die bandwidth at low latency. To achieve next-generation performance requirements and to apply to commercial products, fundamental parameters for 2.5-D Interposers are considered including: 1) high interconnect density at short interconnect length; 2) low power consumption; and 3) low packaging cost. The 2.5-D glass Interposer described in this paper is superior to silicon Interposer in cost and electrical performance, and to organic Interposer in interconnect density. This paper describes a 2.5-D glass Interposer as a ball grid array (BGA) package to achieve high bandwidth at low cost to improve bandwidth per unit watt signal power per unit dollar cost (BWF) compared to both silicon and organic Interposers. Due to its high modulus and excellent surface finish, glass affords ultrafine line lithography to form high-density interconnects comparable to silicon, and the process described in this paper goes beyond silicon back-end-of-line processes by implementing a double-side semi-additive process (SAP) at increased copper layer thickness. This thicker metallization results in reduced conductor losses and improved bandwidth per channel compared to silicon. In addition, the low loss tangent of glass reduces dielectric losses in nets requiring through vias including clock distribution and high-speed off-package signals. Availability of glass in thin panel as well as in roll-to-roll formats beyond 500 mm in size reduces packaging cost compared to 300-mm wafer silicon Interposer. The focus of this paper is on the integration of three enabling technologies: 1) advanced SAP for high-density redistribution layers (RDLs); 2) excimer laser ablation of RDL vias; and 3) fine-pitch thermocompression bonding with copper pillar die assembly—for a 2.5-D glass Interposer at interconnect densities comparable to that of silicon to achieve terabit per second interdie bandwidth at highest BWF.
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measurement and analysis of glass Interposer power distribution network resonance effects on a high speed through glass via channel
IEEE Transactions on Electromagnetic Compatibility, 2016Co-Authors: Youngwoo Kim, Jonghoon J Kim, Kyungjun Cho, Jonghyun Cho, Kiyeong Kim, Subin Kim, Srikrishna Sitaraman, Venky Sundaram, P M Raj, Rao TummalaAbstract:In this paper, we measured and analyzed glass Interposer power distribution network (PDN) resonance effects on a high-speed through glass via (TGV) channel for the first time. To verify the glass Interposer PDN resonance effects on the TGV channel, glass Interposer test vehicles were fabricated. With these test vehicles, glass Interposer PDN impedance, channel loss, far-end crosstalk, and eye diagram are measured. Based on these measurements, glass Interposer PDN resonance effects on the signal integrity of the high-speed TGV channel are analyzed. Due to low loss of the glass substrate, sharp high PDN impedance peaks are generated at the resonance frequencies. High PDN impedance peaks at the PDN resonance frequencies, which affect return current of the TGV channel, increase channel loss, crosstalks, and PDN noise coupling in the frequency domain and degrade eye diagram in the time domain. To suppress these glass Interposer PDN resonance effects, a ground shielded-TGV scheme is proposed. The proposed ground shielded-TGV scheme includes two ground TGVs $200\;{{\mu \text{m}}}$ away from the signal TGV considering the design rules and includes package ground underneath the glass Interposer. Effectiveness of the suggested grounding scheme on the resonance effects suppression is verified with three-dimensional electromagnetic simulation. The proposed shielded-TGV design successfully suppressed the glass Interposer PDN resonance effects that results in the suppression of insertion loss, shielding of the crosstalk, and improvement of the eye diagram of the high-speed TGV channel.
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design modeling fabrication and characterization of 2 5 mu text m redistribution layer traces by advanced semiadditive processes on low cost panel based glass Interposers
IEEE Transactions on Components Packaging and Manufacturing Technology, 2016Co-Authors: Ryuta Furuya, Venky Sundaram, Fuhan Liu, Brett Sawyer, Chandrasekharan Nair, Rao TummalaAbstract:This paper presents the latest advances in extending semiadditive process (SAP) methods to 2–5 $\mu \text{m}$ lines and spaces, achieved using dry film photoresists on thin glass substrates, toward meeting the routing requirements for 20- $\mu \text{m}$ bump pitch Interposers. High-density chip-to-chip interconnections on 2.5-D Interposers are a key enabler to meet the high logic to memory bandwidth needs of next-generation electronic systems. Such 2.5-D Interposers require ultrafine redistribution layer (RDL) traces with line widths and spacing below $5~\mu \text{m}$ . This paper reports on the extension of panel scale and lower cost SAPs to achieve less than $5~\mu \text{m}$ lines and spaces, based on the ultrasmooth surface and improved dimensional stability of thin glass panels. A modified low-cost SAP method with newly developed differential seed layer etching was employed to fabricate the fine line and space patterns and coplanar waveguide (CPW) transmission on thin glass panels. Fine lines down to 2- $\mu \text{m}$ lines and spaces and CPW lines with signal lengths up to 5 mm and ground-to-signal gaps down to $5.5~\mu \text{m}$ at 15- $\mu \text{m}$ signal widths were successfully fabricated on ultra-thin glass panels. For comparison, the same processes were also applied to a silicon wafer. The signal insertion losses of CPW lines on the glass were 0.024 dB/mm better at 15 GHz than those on the silicon, as confirmed by simulations as well as VNA measurements. The measured insertion loss of 5-mm long CPW lines on glass Interposer was 0.7 dB at 10 GHz and matched well to the simulated values.
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design and demonstration of power delivery networks with effective resonance suppression in double sided 3 d glass Interposer packages
IEEE Transactions on Components Packaging and Manufacturing Technology, 2016Co-Authors: Gokul Kumar, Joungho Kim, Jonghyun Cho, Srikrishna Sitaraman, Venky Sundaram, Rao TummalaAbstract:Ultrathin 3-D glass Interposers with through-package vias at the same pitch as through-silicon vias (TSVs) have been proposed as a simpler and cheaper alternative to the direct 3-D stacking of logic and memory devices. Such 3-D Interposers provide wide-I/O channels for high signal bandwidth (BW) between the logic device on one side of the Interposer and memory stack on the other side, without the use of complex TSVs in the logic die. However, this configuration introduces power delivery design challenges due to resonance from: 1) the low-loss property of the glass substrate and 2) the parasitic inductance due to additional length from lateral power delivery path. This paper presents for the first time, the design and demonstration of power delivery networks (PDNs) in 30- $\mu \text{m}$ thin, 3-D double-sided glass Interposers, by suppressing the noise from mode resonances. The self-impedance of the 3-D glass Interposer PDN was simulated using electromagnetic solvers, including printed-wiring-board and chip-level models. The 3-D PDN was compared with that of the 2-D glass packages having fully populated ball grid array connections. The resonance mechanism for each configuration was studied in detail, and the corresponding PDN loop inductances were evaluated. High impedance peaks in addition to the 2-D PDN were observed at high frequencies (near 7.3 GHz) in the 3-D Interposer structure due to the increased inductances from lateral power delivery. This paper proposes and evaluates three important resonance suppression techniques based on: 1) 3-D Interposer die configuration; 2) the selection and placement of decoupling capacitors; and 3) 3-D Interposer package power and ground stack-up. Two-metal and four-metal layer test vehicles were fabricated on 30- and 100- $\mu \text{m}$ thick panel-based glass substrates, respectively, to validate the modeling and analysis of the proposed approach. The PDN test structures were characterized up to 20 GHz for plane resonances and network impedances, with good model-to-hardware correlation. The results in this paper suggest that the ultrathin 3-D Interposer PDN structure can be effectively designed to meet the target impedance guidelines for high-BW applications, providing a compelling alternative to 3-D-IC stacking with the TSVs.
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impact of copper through package vias on thermal performance of glass Interposers
IEEE Transactions on Components Packaging and Manufacturing Technology, 2015Co-Authors: Sangbeom Cho, Rao Tummala, Venky Sundaram, Yogendra JoshiAbstract:In this paper, the thermal performance of glass Interposer substrate with copper through-package vias (TPVs) is investigated both experimentally and numerically. Copper via arrays with different via pitches and diameters were fabricated in 114.3 mm $\times \,\, 114.3$ mm $\times \,\, 100\mu \text{m}$ glass panels using low-cost laser drilling, electroless plating, and electroplating for copper deposition. The thermal performance of such a structure was quantified by measuring an effective thermal conductivity which combines the effect of copper and glass. The effective thermal conductivity of fabricated samples was determined with infrared microscopy and compared with finite-element analysis on unit TPV cell. Using the effective thermal conductivity, further numerical analyses were performed on a 2.5-D Interposer, which has two chips mounted side by side with a total heat generation of 3 W. Interconnects and TPV layers in the Interposer were modeled as homogeneous layers with an effective thermal conductivity. Using the developed model, the effect of copper TPVs on the thermal performance of silicon and glass Interposers was compared. To further characterize the thermal performance of the 2.5-D glass Interposer structure, the effects of pitch of interconnects and TPVs and the TPV diameter are presented.
Harold Barnard - One of the best experts on this subject based on the ideXlab platform.
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joule heating induced thermomigration failure in un powered microbumps due to thermal crosstalk in 2 5d ic technology
Journal of Applied Physics, 2016Co-Authors: Menglu Li, Sam Gu, Dilworth Y Parkinson, Harold Barnard, K N TuAbstract:Thermal-crosstalk induced thermomigration failure in un-powered microbumps has been found in 2.5D integrated circuit (IC) circuit. In 2.5D IC, a Si Interposer was used between a polymer substrate and a device chip which has transistors. The Interposer has no transistors. If transistors are added to the Interposer chip, it becomes 3D IC. In our test structure, there are two Si chips placed horizontally on a Si Interposer. The vertical connections between the Interposer and the Si chips are through microbumps. We powered one daisy chain of the microbumps under one Si chip; however, the un-powered microbumps in the neighboring chip are failed with big holes in the solder layer. We find that Joule heating from the powered microbumps is transferred horizontally to the bottom of the neighboring un-powered microbumps, and creates a large temperature gradient, in the order of 1000 °C/cm, through the un-powered microbumps in the neighboring chip, so the latter failed by thermomigration. In addition, we used synchr...
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joule heating induced thermomigration failure in un powered microbumps due to thermal crosstalk in 2 5d ic technology
Journal of Applied Physics, 2016Co-Authors: Dongwook Kim, Dilworth Y Parkinson, Harold BarnardAbstract:Thermal-crosstalk induced thermomigration failure in un-powered microbumps has been found in 2.5D integrated circuit (IC) circuit. In 2.5D IC, a Si Interposer was used between a polymer substrate and a device chip which has transistors. The Interposer has no transistors. If transistors are added to the Interposer chip, it becomes 3D IC. In our test structure, there are two Si chips placed horizontally on a Si Interposer. The vertical connections between the Interposer and the Si chips are through microbumps. We powered one daisy chain of the microbumps under one Si chip; however, the un-powered microbumps in the neighboring chip are failed with big holes in the solder layer. We find that Joule heating from the powered microbumps is transferred horizontally to the bottom of the neighboring un-powered microbumps, and creates a large temperature gradient, in the order of 1000 °C/cm, through the un-powered microbumps in the neighboring chip, so the latter failed by thermomigration. In addition, we used synchrotron radiation tomography to compare three sets of microbumps in the test structure: microbumps under electromigration, microbumps under thermomigration, and microbumps under a constant temperature thermal annealing. The results show that the microbumps under thermomigration have the largest damage. Furthermore, simulation of temperature distribution in the test structure supports the finding of thermomigration.
Venky Sundaram - One of the best experts on this subject based on the ideXlab platform.
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design and demonstration of a 2 5 d glass Interposer bga package for high bandwidth and low cost
IEEE Transactions on Components Packaging and Manufacturing Technology, 2017Co-Authors: Brett Sawyer, Vanessa Smet, Venky Sundaram, Yuya Suzuki, Ryuta Furuya, Chandrasekharan Nair, Tingchia Huang, Kadappan Panayappan, Rao TummalaAbstract:Consumer demand for mobile services is expected to grow with the continued proliferation of connected devices including smartphones, wearables, and Internet of things. As a result, high-performance computing systems that support the core network and cloud infrastructures for these connected devices require unprecedented die-to-die bandwidth at low latency. To achieve next-generation performance requirements and to apply to commercial products, fundamental parameters for 2.5-D Interposers are considered including: 1) high interconnect density at short interconnect length; 2) low power consumption; and 3) low packaging cost. The 2.5-D glass Interposer described in this paper is superior to silicon Interposer in cost and electrical performance, and to organic Interposer in interconnect density. This paper describes a 2.5-D glass Interposer as a ball grid array (BGA) package to achieve high bandwidth at low cost to improve bandwidth per unit watt signal power per unit dollar cost (BWF) compared to both silicon and organic Interposers. Due to its high modulus and excellent surface finish, glass affords ultrafine line lithography to form high-density interconnects comparable to silicon, and the process described in this paper goes beyond silicon back-end-of-line processes by implementing a double-side semi-additive process (SAP) at increased copper layer thickness. This thicker metallization results in reduced conductor losses and improved bandwidth per channel compared to silicon. In addition, the low loss tangent of glass reduces dielectric losses in nets requiring through vias including clock distribution and high-speed off-package signals. Availability of glass in thin panel as well as in roll-to-roll formats beyond 500 mm in size reduces packaging cost compared to 300-mm wafer silicon Interposer. The focus of this paper is on the integration of three enabling technologies: 1) advanced SAP for high-density redistribution layers (RDLs); 2) excimer laser ablation of RDL vias; and 3) fine-pitch thermocompression bonding with copper pillar die assembly—for a 2.5-D glass Interposer at interconnect densities comparable to that of silicon to achieve terabit per second interdie bandwidth at highest BWF.
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measurement and analysis of glass Interposer power distribution network resonance effects on a high speed through glass via channel
IEEE Transactions on Electromagnetic Compatibility, 2016Co-Authors: Youngwoo Kim, Jonghoon J Kim, Kyungjun Cho, Jonghyun Cho, Kiyeong Kim, Subin Kim, Srikrishna Sitaraman, Venky Sundaram, P M Raj, Rao TummalaAbstract:In this paper, we measured and analyzed glass Interposer power distribution network (PDN) resonance effects on a high-speed through glass via (TGV) channel for the first time. To verify the glass Interposer PDN resonance effects on the TGV channel, glass Interposer test vehicles were fabricated. With these test vehicles, glass Interposer PDN impedance, channel loss, far-end crosstalk, and eye diagram are measured. Based on these measurements, glass Interposer PDN resonance effects on the signal integrity of the high-speed TGV channel are analyzed. Due to low loss of the glass substrate, sharp high PDN impedance peaks are generated at the resonance frequencies. High PDN impedance peaks at the PDN resonance frequencies, which affect return current of the TGV channel, increase channel loss, crosstalks, and PDN noise coupling in the frequency domain and degrade eye diagram in the time domain. To suppress these glass Interposer PDN resonance effects, a ground shielded-TGV scheme is proposed. The proposed ground shielded-TGV scheme includes two ground TGVs $200\;{{\mu \text{m}}}$ away from the signal TGV considering the design rules and includes package ground underneath the glass Interposer. Effectiveness of the suggested grounding scheme on the resonance effects suppression is verified with three-dimensional electromagnetic simulation. The proposed shielded-TGV design successfully suppressed the glass Interposer PDN resonance effects that results in the suppression of insertion loss, shielding of the crosstalk, and improvement of the eye diagram of the high-speed TGV channel.
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design modeling fabrication and characterization of 2 5 mu text m redistribution layer traces by advanced semiadditive processes on low cost panel based glass Interposers
IEEE Transactions on Components Packaging and Manufacturing Technology, 2016Co-Authors: Ryuta Furuya, Venky Sundaram, Fuhan Liu, Brett Sawyer, Chandrasekharan Nair, Rao TummalaAbstract:This paper presents the latest advances in extending semiadditive process (SAP) methods to 2–5 $\mu \text{m}$ lines and spaces, achieved using dry film photoresists on thin glass substrates, toward meeting the routing requirements for 20- $\mu \text{m}$ bump pitch Interposers. High-density chip-to-chip interconnections on 2.5-D Interposers are a key enabler to meet the high logic to memory bandwidth needs of next-generation electronic systems. Such 2.5-D Interposers require ultrafine redistribution layer (RDL) traces with line widths and spacing below $5~\mu \text{m}$ . This paper reports on the extension of panel scale and lower cost SAPs to achieve less than $5~\mu \text{m}$ lines and spaces, based on the ultrasmooth surface and improved dimensional stability of thin glass panels. A modified low-cost SAP method with newly developed differential seed layer etching was employed to fabricate the fine line and space patterns and coplanar waveguide (CPW) transmission on thin glass panels. Fine lines down to 2- $\mu \text{m}$ lines and spaces and CPW lines with signal lengths up to 5 mm and ground-to-signal gaps down to $5.5~\mu \text{m}$ at 15- $\mu \text{m}$ signal widths were successfully fabricated on ultra-thin glass panels. For comparison, the same processes were also applied to a silicon wafer. The signal insertion losses of CPW lines on the glass were 0.024 dB/mm better at 15 GHz than those on the silicon, as confirmed by simulations as well as VNA measurements. The measured insertion loss of 5-mm long CPW lines on glass Interposer was 0.7 dB at 10 GHz and matched well to the simulated values.
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design and demonstration of power delivery networks with effective resonance suppression in double sided 3 d glass Interposer packages
IEEE Transactions on Components Packaging and Manufacturing Technology, 2016Co-Authors: Gokul Kumar, Joungho Kim, Jonghyun Cho, Srikrishna Sitaraman, Venky Sundaram, Rao TummalaAbstract:Ultrathin 3-D glass Interposers with through-package vias at the same pitch as through-silicon vias (TSVs) have been proposed as a simpler and cheaper alternative to the direct 3-D stacking of logic and memory devices. Such 3-D Interposers provide wide-I/O channels for high signal bandwidth (BW) between the logic device on one side of the Interposer and memory stack on the other side, without the use of complex TSVs in the logic die. However, this configuration introduces power delivery design challenges due to resonance from: 1) the low-loss property of the glass substrate and 2) the parasitic inductance due to additional length from lateral power delivery path. This paper presents for the first time, the design and demonstration of power delivery networks (PDNs) in 30- $\mu \text{m}$ thin, 3-D double-sided glass Interposers, by suppressing the noise from mode resonances. The self-impedance of the 3-D glass Interposer PDN was simulated using electromagnetic solvers, including printed-wiring-board and chip-level models. The 3-D PDN was compared with that of the 2-D glass packages having fully populated ball grid array connections. The resonance mechanism for each configuration was studied in detail, and the corresponding PDN loop inductances were evaluated. High impedance peaks in addition to the 2-D PDN were observed at high frequencies (near 7.3 GHz) in the 3-D Interposer structure due to the increased inductances from lateral power delivery. This paper proposes and evaluates three important resonance suppression techniques based on: 1) 3-D Interposer die configuration; 2) the selection and placement of decoupling capacitors; and 3) 3-D Interposer package power and ground stack-up. Two-metal and four-metal layer test vehicles were fabricated on 30- and 100- $\mu \text{m}$ thick panel-based glass substrates, respectively, to validate the modeling and analysis of the proposed approach. The PDN test structures were characterized up to 20 GHz for plane resonances and network impedances, with good model-to-hardware correlation. The results in this paper suggest that the ultrathin 3-D Interposer PDN structure can be effectively designed to meet the target impedance guidelines for high-BW applications, providing a compelling alternative to 3-D-IC stacking with the TSVs.
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impact of copper through package vias on thermal performance of glass Interposers
IEEE Transactions on Components Packaging and Manufacturing Technology, 2015Co-Authors: Sangbeom Cho, Rao Tummala, Venky Sundaram, Yogendra JoshiAbstract:In this paper, the thermal performance of glass Interposer substrate with copper through-package vias (TPVs) is investigated both experimentally and numerically. Copper via arrays with different via pitches and diameters were fabricated in 114.3 mm $\times \,\, 114.3$ mm $\times \,\, 100\mu \text{m}$ glass panels using low-cost laser drilling, electroless plating, and electroplating for copper deposition. The thermal performance of such a structure was quantified by measuring an effective thermal conductivity which combines the effect of copper and glass. The effective thermal conductivity of fabricated samples was determined with infrared microscopy and compared with finite-element analysis on unit TPV cell. Using the effective thermal conductivity, further numerical analyses were performed on a 2.5-D Interposer, which has two chips mounted side by side with a total heat generation of 3 W. Interconnects and TPV layers in the Interposer were modeled as homogeneous layers with an effective thermal conductivity. Using the developed model, the effect of copper TPVs on the thermal performance of silicon and glass Interposers was compared. To further characterize the thermal performance of the 2.5-D glass Interposer structure, the effects of pitch of interconnects and TPVs and the TPV diameter are presented.
Joungho Kim - One of the best experts on this subject based on the ideXlab platform.
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fast and accurate power distribution network modeling of a silicon Interposer for 2 5 d 3 d ics with multiarray tsvs
IEEE Transactions on Components Packaging and Manufacturing Technology, 2019Co-Authors: Kyungjun Cho, Youngwoo Kim, Junyong Park, Subin Kim, Hyunwook Park, Seongsoo Lee, Daeyong Shim, Kangseol Lee, Joungho KimAbstract:In this paper, we first propose power distribution network (PDN) model of the perforated power and ground (P/G) planes including substrate effects and multiarray through-silicon vias (TSVs) for a silicon Interposer. Since it is almost impossible to simulate a high metal density perforated PDN structure, we first suggest a modeling methodology for P/G perforated planes to reduce simulation time significantly with a high accuracy. To obtain the PDN impedance of a silicon Interposer faster, we convert the perforated planes to solid planes with a dielectric mixture. The capacitance (C) and conductance (G) component of perforated P/G planes are precisely estimated based on the conformal mapping method. From the estimated C and G, the physical dimension and material properties of the dielectric mixture of solid P/G planes are determined, respectively. Because silicon Interposer PDN consists of a periodic structure, we design and analyze the unit cell of a PDN thoroughly. From the unit cell analysis, the electrical characteristic of an entire PDN for a silicon Interposer is successfully estimated. The PDN impedance of the proposed solid and perforated P/G planes and simulation time to obtain each PDN impedance are compared and evaluated, respectively. The proposed methodology is validated by a full 3-D electromagnetic (EM) simulation in the frequency range from 0.01 to 20 GHz. We also proposed models of multiarray P/G TSVs that can be applied to the various P/G patterns for a silicon Interposer. From the inductance matrix considering current directions, the self- and mutual inductances of TSVs are accurately calculated. Because quasi-transverse electromagnetic mode is propagated through TSVs and the substrate dielectric of a silicon Interposer can be regarded as a uniform dielectric, the capacitance and conductance of TSVs can be calculated from the inductance matrix. The proposed model of multiarray TSVs is also analyzed and verified by EM simulations in the frequency range from 0.01 to 20 GHz with a high accuracy.
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design and signal integrity analysis of high bandwidth memory hbm Interposer in 2 5d terabyte s bandwidth graphics module
Electrical Design of Advanced Packaging and Systems Symposium, 2016Co-Authors: Hyunsuk Lee, Sumin Choi, Heegon Kim, Jaemin Lim, Kyungjun Cho, Hyunwoo Shim, Joungho KimAbstract:Spurred by the industrial demands for terabyte/s bandwidth graphics module, high bandwidth memory (HBM) has been emerged to overcome the limitations of conventional DRAMs. Additionally, due to the fine pitch and high density interconnect routing between GPU and 4 HBMs in 2.5D terabyte/s bandwidth graphics module, HBM Interposer has also been to the force. However, several signal integrity issues of the HBM Interposer occur due to the manufacturing process constraints. In this paper, we design the HBM Interposer using 6 layers redistribution layer (RDL) and TSVs in 2.5D terabyte/s bandwidth graphics module. And then, in the designed HBM Interposer, electrical performance of the HBM Interposer channels using M1, M3, and M5 layer is analyzed by simulation in the frequency-and time-domain. With the simulation results, it is observed that the designed HBM Interposer shows good signal integrity.
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Signal and power integrity design of 2.5D HBM (High bandwidth memory module) on SI Interposer
2016 Pan Pacific Microelectronics Symposium (Pan Pacific), 2016Co-Authors: Kyungjun Cho, Hyunsuk Lee, Joungho KimAbstract:Spurred by the industrial demands for terabyte/s bandwidth graphics module, high bandwidth memory (HBM) has been emerged to overcome the limitations of conventional DRAMs. Additionally, due to the fine pitch and high density interconnect routing between GPU and 4 HBMs in 2.5D terabyte/s bandwidth graphics module, HBM Interposer has also been to the force. However, several signal integrity issues of the HBM Interposer occur due to the manufacturing process constraints. In this paper, we design the HBM Interposer using 6 layers redistribution layer (RDL) and TSVs in 2.5D terabyte/s bandwidth graphics module. And then, in the designed HBM Interposer, electrical performance of the HBM Interposer channels using M1, M3, and M5 layer is analyzed by simulation in the frequency-and time-domain. With the simulation results, it is observed that the designed HBM Interposer shows good signal integrity.
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design and demonstration of power delivery networks with effective resonance suppression in double sided 3 d glass Interposer packages
IEEE Transactions on Components Packaging and Manufacturing Technology, 2016Co-Authors: Gokul Kumar, Joungho Kim, Jonghyun Cho, Srikrishna Sitaraman, Venky Sundaram, Rao TummalaAbstract:Ultrathin 3-D glass Interposers with through-package vias at the same pitch as through-silicon vias (TSVs) have been proposed as a simpler and cheaper alternative to the direct 3-D stacking of logic and memory devices. Such 3-D Interposers provide wide-I/O channels for high signal bandwidth (BW) between the logic device on one side of the Interposer and memory stack on the other side, without the use of complex TSVs in the logic die. However, this configuration introduces power delivery design challenges due to resonance from: 1) the low-loss property of the glass substrate and 2) the parasitic inductance due to additional length from lateral power delivery path. This paper presents for the first time, the design and demonstration of power delivery networks (PDNs) in 30- $\mu \text{m}$ thin, 3-D double-sided glass Interposers, by suppressing the noise from mode resonances. The self-impedance of the 3-D glass Interposer PDN was simulated using electromagnetic solvers, including printed-wiring-board and chip-level models. The 3-D PDN was compared with that of the 2-D glass packages having fully populated ball grid array connections. The resonance mechanism for each configuration was studied in detail, and the corresponding PDN loop inductances were evaluated. High impedance peaks in addition to the 2-D PDN were observed at high frequencies (near 7.3 GHz) in the 3-D Interposer structure due to the increased inductances from lateral power delivery. This paper proposes and evaluates three important resonance suppression techniques based on: 1) 3-D Interposer die configuration; 2) the selection and placement of decoupling capacitors; and 3) 3-D Interposer package power and ground stack-up. Two-metal and four-metal layer test vehicles were fabricated on 30- and 100- $\mu \text{m}$ thick panel-based glass substrates, respectively, to validate the modeling and analysis of the proposed approach. The PDN test structures were characterized up to 20 GHz for plane resonances and network impedances, with good model-to-hardware correlation. The results in this paper suggest that the ultrathin 3-D Interposer PDN structure can be effectively designed to meet the target impedance guidelines for high-BW applications, providing a compelling alternative to 3-D-IC stacking with the TSVs.
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design optimization of high bandwidth memory hbm Interposer considering signal integrity
Electrical Design of Advanced Packaging and Systems Symposium, 2015Co-Authors: Kyungjun Cho, Sumin Choi, Heegon Kim, Jaemin Lim, Youngwoo Kim, Joungho Kim, Hyunsuk Lee, Hyungsoo Kim, Yongju Kim, Yunsaing KimAbstract:As total system bandwidth increased, memory industry has been imposed to satisfy its requirements. At last, innovative next generation memory named high bandwidth memory (HBM) with extremely fine micro-bump pitch of its bottom die is introduced for terabytes/s bandwidth graphics module. To establish HBM based graphics module, it becomes essential to fabricate silicon Interposer due to its capability to process narrow signal width and space. Silicon based HBM Interposer becomes the key solution to mitigate bandwidth bottleneck of graphics module for high computing system. To design HBM Interposer successfully, the signal optimization of HBM Interposer channels must be preceded thoroughly. In this paper, design optimization of top metal signals of HBM Interposer considering routing feasibility is proposed. In order to analyze channel performance to determine optimal line width and space, frequency domain and time domain simulation are conducted respectively. All the proposed signals in HBM Interposer are analyzed by comparing eye-opening voltage and timing jitter with 3D electromagnetic (EM) simulation results. Based on this proposed optimization design, not only HBM Interposer can be applied to achieve high bandwidth with a less signal distortion but also it can be designed on the basis of a limited routing area.
K N Tu - One of the best experts on this subject based on the ideXlab platform.
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joule heating induced thermomigration failure in un powered microbumps due to thermal crosstalk in 2 5d ic technology
Journal of Applied Physics, 2016Co-Authors: Menglu Li, Sam Gu, Dilworth Y Parkinson, Harold Barnard, K N TuAbstract:Thermal-crosstalk induced thermomigration failure in un-powered microbumps has been found in 2.5D integrated circuit (IC) circuit. In 2.5D IC, a Si Interposer was used between a polymer substrate and a device chip which has transistors. The Interposer has no transistors. If transistors are added to the Interposer chip, it becomes 3D IC. In our test structure, there are two Si chips placed horizontally on a Si Interposer. The vertical connections between the Interposer and the Si chips are through microbumps. We powered one daisy chain of the microbumps under one Si chip; however, the un-powered microbumps in the neighboring chip are failed with big holes in the solder layer. We find that Joule heating from the powered microbumps is transferred horizontally to the bottom of the neighboring un-powered microbumps, and creates a large temperature gradient, in the order of 1000 °C/cm, through the un-powered microbumps in the neighboring chip, so the latter failed by thermomigration. In addition, we used synchr...
