The Experts below are selected from a list of 36672 Experts worldwide ranked by ideXlab platform
A Asenov - One of the best experts on this subject based on the ideXlab platform.
-
impact of metal gate granularity on threshold voltage variability a full scale three dimensional statistical simulation study
IEEE Electron Device Letters, 2010Co-Authors: A R Brown, J R Watling, Niza Mohd Idris, A AsenovAbstract:It has recently become clear that the use of high-κ /metal gate stacks will have a distinct impact on the Intrinsic Parameter variability of the corresponding CMOS devices. The metal gates have a natural granularity, with the work function of each grain depending on its orientation. Here, we present a full-scale 3-D statistical simulation study of the statistical variability induced by this metal gate granularity (MGG). We investigate the effect of grain size on both the magnitude of the variability and the shape of the corresponding statistical distribution. The distributions in threshold voltage due to MGG are analyzed in isolation and in combination with random discrete dopants and line-edge roughness.
-
capturing Intrinsic Parameter fluctuations using the psp compact model
Design Automation and Test in Europe, 2010Co-Authors: Binjie Cheng, S. Roy, Daryoosh Dideban, Negin Moezi, C Millar, G Roy, Xingsheng Wang, A AsenovAbstract:Statistical variability (SV) presents increasing challenges to CMOS scaling and integration at nanometer scales. It is essential that SV information is accurately captured by compact models in order to facilitate reliable variability aware design. Using statistical compact model Parameter extraction for the new industry standard compact model PSP, we investigate the accuracy of standard statistical Parameter generation strategies in statistical circuit simulations. Results indicate that the typical use of uncorrelated normal distribution of the statistical compact model Parameters may introduce considerable errors in the statistical circuit simulations.
-
benchmarking statistical compact modeling strategies for capturing device Intrinsic Parameter fluctuations in bsim4 and psp
IEEE Design & Test of Computers, 2010Co-Authors: Binjie Cheng, S. Roy, Daryoosh Dideban, Negin Moezi, C Millar, G Roy, Xingsheng Wang, A AsenovAbstract:Intrinsic statistical variability (SV) associated with discreteness of charge and granularity of matter is one of limiting factors for CMOS scaling and integration. There are several standard statistical Parameter generation strategies to transfer SV information into compact models, and their accuracy is essential for achieving reliable variability aware design. We investigate the accuracy of these strategies based on the direct statistical compact model Parameter extraction results for industry standard compact models BSIM4 and PSP. Statistical circuit simulation results indicate that the standard assumption for uncorrelated normal distribution of the statistical compact model Parameters may introduce considerable errors in the statistical distribution of circuit figure of merits.
-
impact of Intrinsic Parameter fluctuations on the performance of in0 75ga0 25as implant free mosfets
Semiconductor Science and Technology, 2009Co-Authors: Natalia Seoane, A J Garcialoureiro, M Aldegunde, K Kalna, A AsenovAbstract:We investigate the level of statistical variability in implant free (IF) MOSFETs, which are one of the most promising candidates III–V channels implementation. We report results for the threshold voltage (VT) fluctuations in aggressively scaled IF III–V MOSFETs induced by random discrete dopants in the δ-doping plane obtained using 3D drift–diffusion (D–D) device simulations. The D–D simulator is meticulously calibrated against results obtained from ensemble Monte Carlo device simulations. The simulated 30, 20 and 15 nm gate length In0.75Ga0.25As channel IF transistors exhibit threshold voltage standard deviations of 42, 58 and 61 mV, respectively, at a drain voltage of 0.1 V. At a drain voltage of 0.8 V, the threshold voltage standard deviations increase to 55, 71 and 81 mV, respectively. While the standard deviations of VT in the 30 and 20 nm IF MOSFETs are close to those observed in bulk Si MOSFETs with equivalent gate lengths, the threshold voltage standard deviation in the 15 nm gate length IF MOSFET is lower.
-
evaluation of Intrinsic Parameter fluctuations on 45 32 and 22nm technology node lp n mosfets
European Solid-State Device Research Conference, 2008Co-Authors: Binjie Cheng, A R Brown, S. Roy, C Millar, A AsenovAbstract:The quantitative evaluation of the impact of key sources of statistical variability (SV) are presented for LP nMOSFETs corresponding to 45 nm, 32 nm and 22 nm technology generation transistors with bulk, thin body (TB) SOI and double gate (DG) device architectures respectively. The simulation results indicate that TBSOI and DG are not only resistant to random dopant induced variability, but also are more tolerant to line edge roughness induced variability. Even two technology generations ahead from their bulk counterparts, DG MOSFETs will still have 4 times less variability than bulk devices.
A R Brown - One of the best experts on this subject based on the ideXlab platform.
-
impact of metal gate granularity on threshold voltage variability a full scale three dimensional statistical simulation study
IEEE Electron Device Letters, 2010Co-Authors: A R Brown, J R Watling, Niza Mohd Idris, A AsenovAbstract:It has recently become clear that the use of high-κ /metal gate stacks will have a distinct impact on the Intrinsic Parameter variability of the corresponding CMOS devices. The metal gates have a natural granularity, with the work function of each grain depending on its orientation. Here, we present a full-scale 3-D statistical simulation study of the statistical variability induced by this metal gate granularity (MGG). We investigate the effect of grain size on both the magnitude of the variability and the shape of the corresponding statistical distribution. The distributions in threshold voltage due to MGG are analyzed in isolation and in combination with random discrete dopants and line-edge roughness.
-
evaluation of Intrinsic Parameter fluctuations on 45 32 and 22nm technology node lp n mosfets
European Solid-State Device Research Conference, 2008Co-Authors: Binjie Cheng, A R Brown, S. Roy, C Millar, A AsenovAbstract:The quantitative evaluation of the impact of key sources of statistical variability (SV) are presented for LP nMOSFETs corresponding to 45 nm, 32 nm and 22 nm technology generation transistors with bulk, thin body (TB) SOI and double gate (DG) device architectures respectively. The simulation results indicate that TBSOI and DG are not only resistant to random dopant induced variability, but also are more tolerant to line edge roughness induced variability. Even two technology generations ahead from their bulk counterparts, DG MOSFETs will still have 4 times less variability than bulk devices.
-
Intrinsic Parameter fluctuations due to random grain orientations in high κ gate stacks
Journal of Computational Electronics, 2007Co-Authors: A R Brown, J R Watling, A AsenovAbstract:The use of high-κ material in the gate-stack of future nano-CMOS devices presents a number of technological issues which may degrade the device performance and also lead to Parameter fluctuations between devices. The polycrystalline nature of many high-κ materials may lead to non-uniformity in the dielectric properties across the oxide film, resulting in fluctuations in important device Parameters such as the threshold voltage. Here, the effect of random grain orientation of the high-κ dielectric in the gate stack on Parameter fluctuations in the corresponding nanoscale MOSFETs is investigated.
-
Intrinsic Parameter fluctuations in conventional MOSFETs until the end of the ITRS: A statistical simulation study
Journal of Physics: Conference Series, 2006Co-Authors: Gareth Roy, F. Adamu-lema, A R Brown, Scott Roy, Asen AsenovAbstract:Variability in device characteristics will affect the scaling and integration of next generation nano-CMOS transistors. Intrinsic Parameter fluctuations introduced by random discrete dopants, line edge roughness and oxide thickness fluctuations are among the most important sources of variability. In this paper the variability introduced by the above sources is studied in a set of well scaled MOSFETs with channel lengths of 25, 18, 13, and 9 nm. The effect of each source of Intrinsic Parameter fluctuation is quantified and compared. The random discrete dopants are responsible for the strongest variations followed closely by line edge roughness. The statistical independence of the different sources of fluctuations is also studied in the case of a 35 nm MOSFET.
-
Intrinsic Parameter fluctuations in sub-10nm generation UTB SOI MOSFETs
2006Co-Authors: Khairulmizam Samsudin, F. Adamu-lema, A R Brown, Scott Roy, Asen AsenovAbstract:Ultra Thin Body (UTB) SOI are promising alternatives for extending the MOSFET scaling. However, Intrinsic Parameter fluctuations still remains as one of the major challenges for the ultimate scaling and integration of UTB SOI MOSFETs. In this paper, using 3D statistical numerical simulations we investigate the impact of random discrete dopants, body thickness variations and line edge roughness on the magnitude of Intrinsic Parameter fluctuations in UTB SOI MOSFETs. The UTB devices are scaled to physical channel lengths of 10, 7.5 and 5 nm corresponding to the long term requirements of 2005 edition of the International Technology Roadmap for Semiconductors (ITRS).
Asen Asenov - One of the best experts on this subject based on the ideXlab platform.
-
DATE - Capturing Intrinsic Parameter fluctuations using the PSP compact model
2010 Design Automation & Test in Europe Conference & Exhibition (DATE 2010), 2010Co-Authors: Binjie Cheng, Daryoosh Dideban, Negin Moezi, C Millar, Xingsheng Wang, Asen AsenovAbstract:Statistical variability (SV) presents increasing challenges to CMOS scaling and integration at nanometer scales. It is essential that SV information is accurately captured by compact models in order to facilitate reliable variability aware design. Using statistical compact model Parameter extraction for the new industry standard compact model PSP, we investigate the accuracy of standard statistical Parameter generation strategies in statistical circuit simulations. Results indicate that the typical use of uncorrelated normal distribution of the statistical compact model Parameters may introduce considerable errors in the statistical circuit simulations.
-
Combined sources of Intrinsic Parameter fluctuations in sub-25 nm generation UTB-SOI MOSFETs: A statistical simulation study
Solid-State Electronics, 2007Co-Authors: Khairulmizam Samsudin, F. Adamu-lema, Scott Roy, Andrew R. Brown, Asen AsenovAbstract:The ultra thin body (UTB) SOI architecture offers a promising option to extend MOSFET scaling. However, Intrinsic Parameter fluctuations still remain one of the major challenges for the ultimate scaling and integration of UTB-SOI MOSFETs. In this paper, using 3D statistical numerical simulations, we investigate the impact of random discrete dopants, body thickness variations and line edge roughness on the magnitude of Intrinsic Parameter fluctuations in UTB-SOI MOSFETs. The sources of Intrinsic Parameter fluctuations, which can be separated in simulation, will occur simultaneously within a single MOSFET. To understand the impact of these sources of fluctuation in an actual device, simulations with all sources of Intrinsic Parameter fluctuations acting in combination have also been performed.
-
Analysis of the impact of Intrinsic Parameter fluctuations in a 50 nm InP HEMT
2007 Spanish Conference on Electron Devices, 2007Co-Authors: Natalia Seoane, Antonio J. Garcia-loureiro, Karol Kalna, Asen AsenovAbstract:Intrinsic Parameter fluctuations associated with the discreteness of charge and matter become an important factor when the semiconductor devices are scaled to nanometre dimensions. These effects have a considerable effect on the overall device performance. In this work, we have employed a 3D parallel drift-diffusion device simulator to study the impact of Intrinsic Parameter fluctuations in a 50 nm gate length InP HEMT with an In0.7Ga0.3As channel. After careful calibration of the I-V characteristics obtained from the device simulator against experimental data we carry out a statistical study considering the fluctuations in the delta-doping layer and interface charges as well as Indium content variation in the channel. We have found that the presence of random discrete dopants in the delta-doping layer are the major factor introducing the variations in the drive current.
-
The scalability of 8T-SRAM cells under the influence of Intrinsic Parameter fluctuations
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference, 2007Co-Authors: Binjie Cheng, Scott Roy, Asen AsenovAbstract:Intrinsic Parameter fluctuations are already a limiting factor for 6-transistor SRAM scaling. In order to maintain the benefits of CMOS scaling, new SRAM cell designs are necessary. An 8-transistor SRAM cell structure is investigated and the impact of random doping fluctuations on its read and write noise margins, considering various supply voltages, are discussed. The results demonstrate impressive scalability, and indicate that the scaling window is still open for SRAM in the deca-nanometer regime.
-
Intrinsic Parameter fluctuations in conventional MOSFETs until the end of the ITRS: A statistical simulation study
Journal of Physics: Conference Series, 2006Co-Authors: Gareth Roy, F. Adamu-lema, A R Brown, Scott Roy, Asen AsenovAbstract:Variability in device characteristics will affect the scaling and integration of next generation nano-CMOS transistors. Intrinsic Parameter fluctuations introduced by random discrete dopants, line edge roughness and oxide thickness fluctuations are among the most important sources of variability. In this paper the variability introduced by the above sources is studied in a set of well scaled MOSFETs with channel lengths of 25, 18, 13, and 9 nm. The effect of each source of Intrinsic Parameter fluctuation is quantified and compared. The random discrete dopants are responsible for the strongest variations followed closely by line edge roughness. The statistical independence of the different sources of fluctuations is also studied in the case of a 35 nm MOSFET.
Binjie Cheng - One of the best experts on this subject based on the ideXlab platform.
-
capturing Intrinsic Parameter fluctuations using the psp compact model
Design Automation and Test in Europe, 2010Co-Authors: Binjie Cheng, S. Roy, Daryoosh Dideban, Negin Moezi, C Millar, G Roy, Xingsheng Wang, A AsenovAbstract:Statistical variability (SV) presents increasing challenges to CMOS scaling and integration at nanometer scales. It is essential that SV information is accurately captured by compact models in order to facilitate reliable variability aware design. Using statistical compact model Parameter extraction for the new industry standard compact model PSP, we investigate the accuracy of standard statistical Parameter generation strategies in statistical circuit simulations. Results indicate that the typical use of uncorrelated normal distribution of the statistical compact model Parameters may introduce considerable errors in the statistical circuit simulations.
-
DATE - Capturing Intrinsic Parameter fluctuations using the PSP compact model
2010 Design Automation & Test in Europe Conference & Exhibition (DATE 2010), 2010Co-Authors: Binjie Cheng, Daryoosh Dideban, Negin Moezi, C Millar, Xingsheng Wang, Asen AsenovAbstract:Statistical variability (SV) presents increasing challenges to CMOS scaling and integration at nanometer scales. It is essential that SV information is accurately captured by compact models in order to facilitate reliable variability aware design. Using statistical compact model Parameter extraction for the new industry standard compact model PSP, we investigate the accuracy of standard statistical Parameter generation strategies in statistical circuit simulations. Results indicate that the typical use of uncorrelated normal distribution of the statistical compact model Parameters may introduce considerable errors in the statistical circuit simulations.
-
benchmarking statistical compact modeling strategies for capturing device Intrinsic Parameter fluctuations in bsim4 and psp
IEEE Design & Test of Computers, 2010Co-Authors: Binjie Cheng, S. Roy, Daryoosh Dideban, Negin Moezi, C Millar, G Roy, Xingsheng Wang, A AsenovAbstract:Intrinsic statistical variability (SV) associated with discreteness of charge and granularity of matter is one of limiting factors for CMOS scaling and integration. There are several standard statistical Parameter generation strategies to transfer SV information into compact models, and their accuracy is essential for achieving reliable variability aware design. We investigate the accuracy of these strategies based on the direct statistical compact model Parameter extraction results for industry standard compact models BSIM4 and PSP. Statistical circuit simulation results indicate that the standard assumption for uncorrelated normal distribution of the statistical compact model Parameters may introduce considerable errors in the statistical distribution of circuit figure of merits.
-
evaluation of Intrinsic Parameter fluctuations on 45 32 and 22nm technology node lp n mosfets
European Solid-State Device Research Conference, 2008Co-Authors: Binjie Cheng, A R Brown, S. Roy, C Millar, A AsenovAbstract:The quantitative evaluation of the impact of key sources of statistical variability (SV) are presented for LP nMOSFETs corresponding to 45 nm, 32 nm and 22 nm technology generation transistors with bulk, thin body (TB) SOI and double gate (DG) device architectures respectively. The simulation results indicate that TBSOI and DG are not only resistant to random dopant induced variability, but also are more tolerant to line edge roughness induced variability. Even two technology generations ahead from their bulk counterparts, DG MOSFETs will still have 4 times less variability than bulk devices.
-
impact of Intrinsic Parameter fluctuations in nano cmos devices on circuits and systems
International Journal of High Speed Electronics and Systems, 2007Co-Authors: S. Roy, Binjie Cheng, A AsenovAbstract:Device Parameter fluctuations, which arise from both the stochastic nature of the manufacturing process and more fundamentally from the Intrinsic discreteness of charge and matter, are a dominant source of device mismatch in nano-CMOS devices, and a bottleneck to the future yield and performance of circuits and systems. The impact of such Parameter fluctuations is investigated for circuits — with a specific exemplar of 6-T SRAM — whose devices scale from 35 nm gate length. We posit a change in design approach to include the use of statistical compact models as a starting point for the development of cell libraries containing fluctuation information necessary for design under the constraints of Parameter fluctuations, and novel Technology Aided System Design tools.
Scott Roy - One of the best experts on this subject based on the ideXlab platform.
-
The scalability of 8T-SRAM cells under the influence of Intrinsic Parameter fluctuations
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference, 2007Co-Authors: Binjie Cheng, Scott Roy, Asen AsenovAbstract:Intrinsic Parameter fluctuations are already a limiting factor for 6-transistor SRAM scaling. In order to maintain the benefits of CMOS scaling, new SRAM cell designs are necessary. An 8-transistor SRAM cell structure is investigated and the impact of random doping fluctuations on its read and write noise margins, considering various supply voltages, are discussed. The results demonstrate impressive scalability, and indicate that the scaling window is still open for SRAM in the deca-nanometer regime.
-
Combined sources of Intrinsic Parameter fluctuations in sub-25 nm generation UTB-SOI MOSFETs: A statistical simulation study
Solid-State Electronics, 2007Co-Authors: Khairulmizam Samsudin, F. Adamu-lema, Scott Roy, Andrew R. Brown, Asen AsenovAbstract:The ultra thin body (UTB) SOI architecture offers a promising option to extend MOSFET scaling. However, Intrinsic Parameter fluctuations still remain one of the major challenges for the ultimate scaling and integration of UTB-SOI MOSFETs. In this paper, using 3D statistical numerical simulations, we investigate the impact of random discrete dopants, body thickness variations and line edge roughness on the magnitude of Intrinsic Parameter fluctuations in UTB-SOI MOSFETs. The sources of Intrinsic Parameter fluctuations, which can be separated in simulation, will occur simultaneously within a single MOSFET. To understand the impact of these sources of fluctuation in an actual device, simulations with all sources of Intrinsic Parameter fluctuations acting in combination have also been performed.
-
Intrinsic Parameter fluctuations in conventional MOSFETs until the end of the ITRS: A statistical simulation study
Journal of Physics: Conference Series, 2006Co-Authors: Gareth Roy, F. Adamu-lema, A R Brown, Scott Roy, Asen AsenovAbstract:Variability in device characteristics will affect the scaling and integration of next generation nano-CMOS transistors. Intrinsic Parameter fluctuations introduced by random discrete dopants, line edge roughness and oxide thickness fluctuations are among the most important sources of variability. In this paper the variability introduced by the above sources is studied in a set of well scaled MOSFETs with channel lengths of 25, 18, 13, and 9 nm. The effect of each source of Intrinsic Parameter fluctuation is quantified and compared. The random discrete dopants are responsible for the strongest variations followed closely by line edge roughness. The statistical independence of the different sources of fluctuations is also studied in the case of a 35 nm MOSFET.
-
Impact of Intrinsic Parameter Fluctuations on SRAM Cell Design
2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings, 2006Co-Authors: Binjie Cheng, Scott Roy, Asen AsenovAbstract:Intrinsic Parameter fluctuations, arising from the granular nature of charge and matter, are predicted to be a critical roadblock to the future CMOS 6-T SRAM scaling. A hierarchal simulation methodology, which can fully collate Intrinsic Parameter fluctuation information into compact model sets, is employed to investigate the impact of random dopant fluctuation on SRAM static noise margin, and the bias control technology is introduced as a possible solution to improve the SRAM's immunity to Intrinsic Parameter fluctuation
-
Intrinsic Parameter fluctuations in sub-10nm generation UTB SOI MOSFETs
2006Co-Authors: Khairulmizam Samsudin, F. Adamu-lema, A R Brown, Scott Roy, Asen AsenovAbstract:Ultra Thin Body (UTB) SOI are promising alternatives for extending the MOSFET scaling. However, Intrinsic Parameter fluctuations still remains as one of the major challenges for the ultimate scaling and integration of UTB SOI MOSFETs. In this paper, using 3D statistical numerical simulations we investigate the impact of random discrete dopants, body thickness variations and line edge roughness on the magnitude of Intrinsic Parameter fluctuations in UTB SOI MOSFETs. The UTB devices are scaled to physical channel lengths of 10, 7.5 and 5 nm corresponding to the long term requirements of 2005 edition of the International Technology Roadmap for Semiconductors (ITRS).
