The Experts below are selected from a list of 7395 Experts worldwide ranked by ideXlab platform
Vojko Matko - One of the best experts on this subject based on the ideXlab platform.
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major improvements of quartz crystal pulling sensitivity and linearity using series reactance
Sensors, 2009Co-Authors: Vojko Matko, Riko SafaricAbstract:This paper presents a new method of substantially improving frequency pullability and linearity using reactance in series with an AT fundamental crystal operated with a series Load Capacitance in the range of 3 to 50 pF and frequencies in the range of 3.5 to 21 MHz. The research describes high quartz pullability and linearity by varying the Load Capacitance. The paper also gives impedance circuits for crystal unit (3.5 MHz) together with Load Capacitance and compensation reactance. The experimental results show that the new approach using compensation method of quartz crystal connected in series reactance increases the frequency pulling range by ×25 to ×100 depending on the type of oscillator and compensation factor ˝k˝ in the temperature range of 10 to 40 °C.
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a comparison of frequency pullability in oscillators using a single at cut quartz crystal and those using two single at cut crystals connected in parallel with a series Load Capacitance or series Load inductance
Sensors, 2006Co-Authors: Vojko MatkoAbstract:This paper presents a comparison of frequency pullability in oscillators using asingle AT-cut crystal and those using two single AT-cut crystals connected in paralleloperated with a series Load Capacitance or series Load inductance at fundamental frequenciesof 4, 10 and 19 MHz. Pullability describes how the operating frequency may be changed byvarying the Load Capacitance. The paper also gives impedance circuits for both single- anddual-crystal units. The experiment results show that the new approach using two singlequartz crystals connected in parallel increases the frequency pulling range by 30-200% pending on the type of oscillator. Also given is the crystal frequency stability at thesethree frequencies.
Pak Kwong Chan - One of the best experts on this subject based on the ideXlab platform.
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a fvf ldo regulator with dual summed miller frequency compensation for wide Load Capacitance range applications
IEEE Transactions on Circuits and Systems, 2014Co-Authors: Xiao Liang Tan, Sau Siong Chong, Kuan Chuang Koay, Pak Kwong ChanAbstract:This paper presents a proposed Flipped Voltage Follower (FVF) based output capacitorless low-dropout (OCL-LDO) regulator using Dual-Summed Miller Frequency Compensation (DSMFC) technique. Validated by UMC 65-nm CMOS process, the simulation results have shown that the proposed LDO regulator can be stabilized by a total compensation Capacitance (CC) of 8 pF for a Load Capacitance (CL) ranging from 10 pF to 10 nF. It consumes 23.7 μA quiescent current with a 1.2 V supply voltage. With a dropout voltage of 200 mV, the LDO regulator can support a maximum 50 mA Load current. It can settle in less than 1.7 μs with a 1% accuracy for the whole CL range. The proposed LDO regulator is comparable to other reported works in terms of figure-of-merit (FOM). Most significantly, it can drive the widest range of CL and achieve the highest CL(max)/CC ratio with respect to the counterparts.
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a fvf based output capacitorless ldo regulator with wide Load Capacitance range
International Symposium on Circuits and Systems, 2013Co-Authors: Kuan Chuang Koay, Sau Siong Chong, Pak Kwong ChanAbstract:An output capacitorless low-dropout (LDO) regulator, which applies the proposed Dual Summed Miller Frequency Compensation (DSMFC) on Flipped Voltage Follower (FVF) structure with composite power transistor, is proposed. Validated by UMC 65nm CMOS process, the simulation results have shown that the proposed LDO regulator consumes only 13.2μA at a 1.2V supply, with a dropout voltage of 200mV. At a total of 10pF compensation Capacitance, it can support 0-50mA Load current for a Load Capacitance range of 10pF-100nF at typical process and temperature whilst 10pF-10nF at worst condition. The proposed LDO regulator is able to recover in 0.925μs at CL=50pF. The comparison results have shown that the maximum Load Capacitance is more than two orders of magnitude with respect to those of the FVF LDO counterparts at identical process, supply, quiescent power and compensation Capacitance.
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cross feedforward cascode compensation for low power three stage amplifier with large capacitive Load
IEEE Journal of Solid-state Circuits, 2012Co-Authors: Sau Siong Chong, Pak Kwong ChanAbstract:An area-efficient cross feedforward cascode compensation (CFCC) technique is presented for a three-stage amplifier. The proposed amplifier is capable of driving heavy capacitive Load at low power consumption but not dedicated to heavy Load currents or heavy resistive Loading. The CFCC technique enables the nondominant complex poles of the amplifier to be located at high frequencies, resulting in bandwidth extension. The amplifier can be stabilized with a cascode compensation capacitor of only 1.15 pF when driving a 500-pF capacitive Load, greatly reducing the overall area of the amplifier. In addition, the presence of two left-hand-plane (LHP) zeros in the proposed scheme improves the phase margin and relaxes the stability criteria. The proposed technique has been implemented and fabricated in a UMC 65-nm CMOS process and it achieves a 2-MHz gain-bandwidth product (GBW) when driving a 500-pF capacitive Load by consuming only 20.4 μW at a 1.2-V supply. The proposed compensation technique compares favorably in terms of figures-of-merit (FOM) to previously reported works. Most significantly, the CFCC amplifier achieves the highest Load Capacitance to total compensation Capacitance ratio (CL/CT) of all its counterparts.
E Sanchezsinencio - One of the best experts on this subject based on the ideXlab platform.
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design of three stage class ab 16 omega headphone driver capable of handling wide range of Load Capacitance
IEEE Journal of Solid-state Circuits, 2009Co-Authors: V Dhanasekaran, J Silvamartinez, E SanchezsinencioAbstract:In this paper, the effect of Load Capacitance variation on the location of the closed loop poles of three-stage amplifiers is analyzed and a frequency compensation scheme that automatically adjusts the damping factor according to the Load Capacitance is proposed. A class-AB 16 Omega headphone driver designed using the proposed scheme in 0.13 mum technology can handle 1 pF to 22 nF capacitive Load while consuming as low as 1.2 mW of quiescent power. It can deliver a peak power of 40 mW (1.6 Vpp swing) to the Load with - 84.8 dB THD and 92 dB peak SNR. It occupies 0.1 mm2 area.
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a 1 2mw 1 6v pp swing class ab 16ω headphone driver capable of handling Load Capacitance up to 22nf
International Solid-State Circuits Conference, 2008Co-Authors: V Dhanasekaran, J Silvamartinez, E SanchezsinencioAbstract:We present a compensation scheme with a damping circuit that automatically adjusts according to the Load condition to overcome this problem and still maintain the power efficiency improvement over NMC. Capacitive Loads as large as 20nF are used in some platforms for ESD protection and EMI suppression. Several compensation schemes for 3-stage amplifiers driving large capacitive Loads with power efficiency more than 10 times that of the conventional nested Miller compensation (NMC) scheme have been reported recently.
Mansun Chan - One of the best experts on this subject based on the ideXlab platform.
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three dimensional cmos soi integrated circuit using high temperature metal induced lateral crystallization
IEEE Transactions on Electron Devices, 2001Co-Authors: Victor Chan, P C H Chan, Mansun ChanAbstract:A three-dimensional (3-D) CMOS integrated circuit was fabricated based on the conventional CMOS SOI technology. The first layer of transistors was formed on the SOI. The second layer of transistors was built on large-grain polysilicon-on-insulator (LPSOI). The recrystallized film was formed by the recrystallization of amorphous silicon using metal-induced lateral crystallization (MILC). The devices from the lower and upper layers were characterized and the result indicated that the SOI and LPSOI devices have similar electrical characteristics. The 3-D circuit design and layout considerations are introduced. The 3-D CMOS inverters were demonstrated with p-channel devices stacking over the n-channel ones. The ring-oscillator showed that the 3-D circuit has 30% reduction in the layout area and it operated at power supply as low as 0.5 V. The lower propagation delay and Load Capacitance suggest that 3-D circuit has higher performance than the conventional two-dimensional (2-D) circuit.
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on the power dissipation in dynamic threshold silicon on insulator cmos inverter
IEEE Transactions on Electron Devices, 1998Co-Authors: Wei Jin, C H Chan, Mansun ChanAbstract:A power dissipation model for SOI dynamic threshold voltage MOSFET (DTMOS) inverter is proposed for the first time. The model includes static, switching and short-circuit power dissipation. For the switching power dissipation, we have considered both the Load Capacitance and the device parasitic Capacitances. Modeling of the short-circuit power dissipation is based on long-channel DC model for simplicity. The comparison of power dissipation and gate delay between conventional SOI CMOS and SOI DTMOS inverters concludes that DTMOS inverter is better in performance while consumes more power, and its advantage over floating-body SOI inverter diminishes as the power supply approaches 0.7 V.
Haigang Feng - One of the best experts on this subject based on the ideXlab platform.
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a fully integrated fvf based low dropout regulator with wide Load Capacitance and current ranges
IEEE Transactions on Power Electronics, 2019Co-Authors: Mo Huang, Haigang FengAbstract:The flipped-voltage-follower-based low-dropout regulator (LDO) has drawn attention for its fast response and reduced complexity, while super source follower can be combined to push the pole at the gate of the pass device to high frequency. But the maximum Load current and minimum Load Capacitance of this topology are limited, especially when the poles and zero from the SSF are omitted in previous designs. This paper proposes a solution to extend the ranges of the Load current and Load Capacitance, by implementing a small feed-forward capacitor ( $C_{F}$ ) and a damping factor control circuitry. In addition, a slew rate enhancement circuit is applied to reduce the voltage undershoot. The proposed LDO is verified in a 65-nm CMOS process with 0.008 mm2 active area. The measured voltage undershoot is 80 mV with a Load steps from 100 μ A to 50 mA with 2-ns edge times, with no external capacitor. And the maximum Load Capacitance can be extended to 2 nF. A figure-of-merit of 0.8 mV is achieved.