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D L Kwong - One of the best experts on this subject based on the ideXlab platform.
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Three-Layer laminated Metal Gate electrodes with tunable work functions for CMOS applications
IEEE Electron Device Letters, 2005Co-Authors: S. Mathew, Natesan Balasubramanian, L. K. Bera, M. F. Li, N. Yamada, D L KwongAbstract:This letter presents a novel technique for tuning the work function of a Metal Gate electrode. Laminated Metal Gate electrodes consisting of three ultrathin (/spl sim/1-nm) layers, with Metal nitrides (HfN, TiN, or TaN) as the bottom and top layers and element Metals (Hf, Ti, or Ta) as the middle layer, were sequentially deposited on SiO/sub 2/, followed by rapid thermal annealing annealing. Annealing of the laminated Metal Gate stacks at high temperatures (800/spl deg/C-1000/spl deg/C) drastically increased their work functions (as much as 1 eV for HfN-Ti-TaN at 1000/spl deg/C). On the contrary, the bulk Metal Gate electrodes (HfN, TiN and TaN) exhibited consistent midgap work functions with only slight variation under identical annealing conditions. The work function change of the laminated Metal electrodes is attributed to the crystallization and the grain boundary effect of the laminated structures after annealing. This change is stable and not affected by subsequent high-temperature process. The three-layer laminated Metal Gate technique provides PMOS-compatible work functions and excellent thermal stability even after annealing at 1000/spl deg/C.
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Thermally robust TaTb/sub x/N Metal Gate electrode for n-MOSFETs applications
IEEE Electron Device Letters, 2005Co-Authors: H Y Yu, X.p. Wang, D.s.h. Chan, M. F. Li, C.h. Tung, N. Balasubramanian, A.c.h. Huan, D L KwongAbstract:In this letter, we study Terbium (Tb)-incorporated TaN (TaTb/sub x/N) as a thermally robust N-type Metal Gate electrode for the first time. The work function of the Ta/sub 0.94/Tb/sub 0.06/N/sub y/ Metal Gate is determined to be /spl sim/4.23 eV after rapid thermal anneal at 1000/spl deg/C for 30 s, and can be further tuned by varying the Tb concentration. Moreover, the TaTb/sub x/N-SiO/sub 2/ Gate stack exhibits excellent thermal stability up to 1000/spl deg/C with no degradation to the equivalent oxide thickness, Gate leakage, and time-dependent dielectric breakdown (TDDB) characteristics. These results suggest that Tb-incorporated TaN (TaTb/sub x/N) could be a promising Metal Gate candidate for n-MOSFET in a dual-Metal Gate Si CMOS process.
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substituted aluminum Metal Gate on high k dielectric for low work function and fermi level pinning free
International Electron Devices Meeting, 2004Co-Authors: Chang Seo Park, Lei Jun Tang, D L KwongAbstract:Substituted aluminum (SA) Metal Gate on high-K Gate dielectric is successfully demonstrated. Full substitution of polysilicon with Al is achieved in Ti/Al/polysilicon/HfAlON Gate structure by a low temperature annealing at 450/spl deg/C. The SA Gate on HfAlON dielectric shows a very low work function of 4.25 eV, which is well suitable for bulk nMOSFETs. The SA process is fully free from Fermi level pinning problem. In addition, the SA process also shows improved uniformity in leakage current distribution compared to fully silicided (FUSI) Metal Gate.
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Fermi pinning-induced thermal instability of Metal-Gate work functions
IEEE Electron Device Letters, 2004Co-Authors: H Y Yu, J.f. Kang, X.p. Wang, D.s.h. Chan, Ming-fu Li, D L KwongAbstract:The dependence of the Metal-Gate work function on the annealing temperature is experimentally studied. We observe increased Fermi-level pinning of the Metal-Gate work function with increased annealing temperature. This effect is more significant for SiO/sub 2/ than for HfO/sub 2/ Gate dielectric. A Metal-dielectric interface model that takes the role of extrinsic states into account is proposed to explain the work function thermal instability. This letter provides new understanding on work function control for Metal-Gate transistors and on Metal-dielectric interfaces.
Matthew Hillsboro Metz - One of the best experts on this subject based on the ideXlab platform.
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high spl kappa Metal Gate stack and its mosfet characteristics
IEEE Electron Device Letters, 2004Co-Authors: R. Chau, Suman Datta, Mark L. Doczy, Jack Kavalieros, B. Doyle, Matthew Hillsboro MetzAbstract:We show experimental evidence of surface phonon scattering in the high-/spl kappa/ dielectric being the primary cause of channel electron mobility degradation. Next, we show that midgap TiN Metal-Gate electrode is effective in screening phonon scattering in the high-/spl kappa/ dielectric from coupling to the channel under inversion conditions, resulting in improved channel electron mobility. We then show that other Metal-Gate electrodes, such as the ones with n+ and p+ work functions, are also effective in improving channel mobilities to close to those of the conventional SiO/sub 2//poly-Si stack. Finally, we demonstrate this mobility degradation recovery translates directly into high drive performance on high-/spl kappa//Metal-Gate CMOS transistors with desirable threshold voltages.
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High-/spl kappa//Metal-Gate stack and its MOSFET characteristics
IEEE Electron Device Letters, 2004Co-Authors: R. Chau, Suman Datta, Mark L. Doczy, Jack Kavalieros, B. Doyle, Matthew Hillsboro MetzAbstract:We show experimental evidence of surface phonon scattering in the high-/spl kappa/ dielectric being the primary cause of channel electron mobility degradation. Next, we show that midgap TiN Metal-Gate electrode is effective in screening phonon scattering in the high-/spl kappa/ dielectric from coupling to the channel under inversion conditions, resulting in improved channel electron mobility. We then show that other Metal-Gate electrodes, such as the ones with n+ and p+ work functions, are also effective in improving channel mobilities to close to those of the conventional SiO/sub 2//poly-Si stack. Finally, we demonstrate this mobility degradation recovery translates directly into high drive performance on high-/spl kappa//Metal-Gate CMOS transistors with desirable threshold voltages.
Dim-lee Kwong - One of the best experts on this subject based on the ideXlab platform.
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Metal Gate work function engineering on Gate leakage of MOSFETs
IEEE Transactions on Electron Devices, 2004Co-Authors: Y.t. Hou, Tony Low, Dim-lee KwongAbstract:We present a systematic study of tunneling leakage current in Metal Gate MOSFETs and how it is affected by the work function of the Metal Gate electrodes. Physical models used for simulations were corroborated by experimental results from SiO/sub 2/ and HfO/sub 2/ Gate dielectrics with TaN electrodes. In bulk CMOS results show that, at the same capacitance equivalent oxide thickness (CET) at inversion, replacing a poly-Si Gate by Metal reduces the Gate leakage appreciably by one to two orders of magnitude due to the elimination of polysilicon Gate depletion. It is also found that the work function /spl Phi//sub B/ of a Metal Gate affects tunneling characteristics in MOSFETs. It is particularly significant when the transistor is biased at accumulation. Specifically, the increase of /spl Phi//sub B/ reduces the Gate-to-channel tunneling in off-biased n-FET and the use of a Metal Gate with midgap /spl Phi//sub B/ results in a significant reduction of Gate to source/drain extension (SDE) tunneling in both n- and p-FETs. Compared to bulk FET, double Gate (DG) FET has much lower off-state leakage due to the smaller Gate to SDE tunneling. This reduction in off-state leakage can be as much as three orders of magnitude when high-/spl kappa/ Gate dielectric is used. Finally, the benefits of employing Metal Gate DG structure in future CMOS scaling are discussed.
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Laminated Metal Gate electrode with tunable work function for advanced CMOS
Digest of Technical Papers. 2004 Symposium on VLSI Technology 2004., 2004Co-Authors: S.h. Bae, L. K. Bera, N. Yamada, S. Mathew, Huang-chun Wen, N. Balasubramanian, Weiping Bai, Dim-lee KwongAbstract:This paper presents a novel technique for tuning the work function of Metal Gate electrodes. Laminated Metal Gate electrodes consisting of 1/spl sim/3 ultra thin (/spl sim/10 /spl Aring/) layers of Ta, TaN, Ti, TiN, Hf or HfN and bulk Metal nitride Gate electrodes were deposited on SiO/sub 2/, HfO/sub 2/ or HfON, followed by RTP annealing to evaluate their thermal stability. Our results show that the work function of the laminated Metal Gate electrodes is significantly different from their bulk electrodes counterpart. Through lamination, a TiTaN/sub x/ alloy Gate is formed which exhibits NMOS compatible work function (4.35 eV) with good thermal stability up to 900/spl deg/C. Laminated Metal Gates consisting of 3 components exhibit pMOS compatible work function (5,0/spl sim/5.2 eV) after 1000/spl deg/C annealing and this value remains unchanged after subsequent thermal processing. Possible mechanism responsible for work function tuning using laminated Gates is discussed.
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Impact of Metal Gate work function on nano CMOS device performance
Proceedings. 7th International Conference on Solid-State and Integrated Circuits Technology 2004., 1Co-Authors: Y.t. Hou, Tony Low, G. Samudra, Dim-lee KwongAbstract:We studied two effects in the Metal Gate work function engineering in nano CMOSFETs: (1) Gate work function shifts induced by carrier quantization in Si and Ge ultra-thin body FETs with sub-10 nm body thickness and different surface orientations. Guidelines for Metal Gate work function engineering are provided and technical challenges identified; (2) we presented a systematic study on Gate tunneling characteristics of Metal Gate CMOSFETs. A reduction of Gate to source/drain extension tunneling is found when using near mid-gap Metal Gate in SOI CMOS, especially when using high-K dielectric. Benefits of this reduction to transistor off-state leakage and to future CMOS scaling were analyzed.
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Impact of Metal Gate work function on Gate leakage of MOSFETs
International Semiconductor Device Research Symposium 2003, 1Co-Authors: Y.t. Hou, Tony Low, Dim-lee KwongAbstract:A systematic study of tunneling leakage current in Metal Gate MOFETs is carried out and the physical model used were corroborated by experiments. Effects of Metal Gate work function on tunnelling characteristics and the criterion for choosing suitable Metal Gate results in significant reduction of Gate-SDE tunnelling. As a result, SOI FETs exhibit much lower off-state leakage than the bulk ones, particularly for high-K dielectric, indicating their superior scalability in terms of leakage currents.
H Y Yu - One of the best experts on this subject based on the ideXlab platform.
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Thermally robust TaTb/sub x/N Metal Gate electrode for n-MOSFETs applications
IEEE Electron Device Letters, 2005Co-Authors: H Y Yu, X.p. Wang, D.s.h. Chan, M. F. Li, C.h. Tung, N. Balasubramanian, A.c.h. Huan, D L KwongAbstract:In this letter, we study Terbium (Tb)-incorporated TaN (TaTb/sub x/N) as a thermally robust N-type Metal Gate electrode for the first time. The work function of the Ta/sub 0.94/Tb/sub 0.06/N/sub y/ Metal Gate is determined to be /spl sim/4.23 eV after rapid thermal anneal at 1000/spl deg/C for 30 s, and can be further tuned by varying the Tb concentration. Moreover, the TaTb/sub x/N-SiO/sub 2/ Gate stack exhibits excellent thermal stability up to 1000/spl deg/C with no degradation to the equivalent oxide thickness, Gate leakage, and time-dependent dielectric breakdown (TDDB) characteristics. These results suggest that Tb-incorporated TaN (TaTb/sub x/N) could be a promising Metal Gate candidate for n-MOSFET in a dual-Metal Gate Si CMOS process.
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Fermi pinning-induced thermal instability of Metal-Gate work functions
IEEE Electron Device Letters, 2004Co-Authors: H Y Yu, J.f. Kang, X.p. Wang, D.s.h. Chan, Ming-fu Li, D L KwongAbstract:The dependence of the Metal-Gate work function on the annealing temperature is experimentally studied. We observe increased Fermi-level pinning of the Metal-Gate work function with increased annealing temperature. This effect is more significant for SiO/sub 2/ than for HfO/sub 2/ Gate dielectric. A Metal-dielectric interface model that takes the role of extrinsic states into account is proposed to explain the work function thermal instability. This letter provides new understanding on work function control for Metal-Gate transistors and on Metal-dielectric interfaces.
R. Chau - One of the best experts on this subject based on the ideXlab platform.
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high spl kappa Metal Gate stack and its mosfet characteristics
IEEE Electron Device Letters, 2004Co-Authors: R. Chau, Suman Datta, Mark L. Doczy, Jack Kavalieros, B. Doyle, Matthew Hillsboro MetzAbstract:We show experimental evidence of surface phonon scattering in the high-/spl kappa/ dielectric being the primary cause of channel electron mobility degradation. Next, we show that midgap TiN Metal-Gate electrode is effective in screening phonon scattering in the high-/spl kappa/ dielectric from coupling to the channel under inversion conditions, resulting in improved channel electron mobility. We then show that other Metal-Gate electrodes, such as the ones with n+ and p+ work functions, are also effective in improving channel mobilities to close to those of the conventional SiO/sub 2//poly-Si stack. Finally, we demonstrate this mobility degradation recovery translates directly into high drive performance on high-/spl kappa//Metal-Gate CMOS transistors with desirable threshold voltages.
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High-/spl kappa//Metal-Gate stack and its MOSFET characteristics
IEEE Electron Device Letters, 2004Co-Authors: R. Chau, Suman Datta, Mark L. Doczy, Jack Kavalieros, B. Doyle, Matthew Hillsboro MetzAbstract:We show experimental evidence of surface phonon scattering in the high-/spl kappa/ dielectric being the primary cause of channel electron mobility degradation. Next, we show that midgap TiN Metal-Gate electrode is effective in screening phonon scattering in the high-/spl kappa/ dielectric from coupling to the channel under inversion conditions, resulting in improved channel electron mobility. We then show that other Metal-Gate electrodes, such as the ones with n+ and p+ work functions, are also effective in improving channel mobilities to close to those of the conventional SiO/sub 2//poly-Si stack. Finally, we demonstrate this mobility degradation recovery translates directly into high drive performance on high-/spl kappa//Metal-Gate CMOS transistors with desirable threshold voltages.
