The Experts below are selected from a list of 360 Experts worldwide ranked by ideXlab platform
Sung Min Yoon - One of the best experts on this subject based on the ideXlab platform.
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effects of thickness and geometric variations in the oxide gate stack on the Nonvolatile Memory behaviors of charge trap Memory thin film transistors
Solid-state Electronics, 2015Co-Authors: Jun Yong Bak, Chun Won Byun, Chi-sun Hwang, Minki Ryu, Sojung Kim, Sung Min YoonAbstract:Abstract Device designs of charge-trap oxide Memory thin-film transistors (CTM-TFTs) were investigated to enhance their Nonvolatile Memory performances. The first strategy was to optimize the film thicknesses of the tunneling and charge-trap (CT) layers in order to meet requirements of both higher operation speed and longer retention time. While the program speed and Memory window were improved for the device with a thinner tunneling layer, a long retention time was obtained only for the device with a tunneling layer thicker than 5 nm. The carrier concentration and charge-trap densities were optimized in the 30-nm-thick CT layer. It was observed that 10-nm-thick tunneling, 30-nm-thick CT, and 50-nm-thick blocking layers were the best configuration for our proposed CTM-TFTs, where a Memory on/off margin higher than 10 7 was obtained, and a Memory margin of 6.6 × 10 3 was retained even after the lapse of 10 5 s. The second strategy was to examine the effects of the geometrical relations between the CT and active layers for the applications of Memory elements embedded in circuitries. The CTM-TFTs fabricated without an overlap between the CT layer and the drain electrode showed an enhanced program speed by the reduced parasitic capacitance. The drain-bias disturbance for the Memory off-state was effectively suppressed even when a higher read-out drain voltage was applied. Appropriate device design parameters, such as the film thicknesses of each component layer and the geometrical relations between them, can improve the Memory performances and expand the application fields of the proposed CTM-TFTs.
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oxide semiconductor based organic inorganic hybrid dual gate Nonvolatile Memory thin film transistor
IEEE Transactions on Electron Devices, 2011Co-Authors: Sung Min Yoon, Shin Hyuk Yang, Chun Won Byun, Soon-won Jung, Chi-sun Hwang, Sanghee Ko Park, Minki Ryu, Kyoungik ChoAbstract:An organic/inorganic hybrid dual-gate (DG) Nonvolatile Memory thin-film transistor (M-TFT) was proposed as a device with high potential for implementing large-area electronics on flexible and/or transparent substrates. The active channel and bottom and top gate insulators (GIs) of the M-TFT were composed of In-Ga-Zn-O, Al2O3, and poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)], respectively. It was confirmed that the fabricated DG M-TFT showed excellent device characteristics, in which the obtained field-effect mobility, subthreshold swing, and on/off ratio were approximately 32.1 cm2 V-1 s-1, 0.13 V/dec, and 108, respectively. It was also successfully demonstrated that the DG configuration for the proposed M-TFT could effectively work for improving the device controllability by individually controlling the bias conditions of the top gate and bottom gate (BG). The turn-on voltage could be dynamically modulated and controlled when an appropriate fixed negative voltage was applied to the BG. The required duration of the programming pulse to obtain a Memory margin of more than 10 could be reduced to 100 μs. These results correspond to the first demonstration of a hybrid-type DG M-TFT using a ferroelectric copolymer GI/oxide semiconducting active channel structure and demonstrate the feasibility of a promising Memory device embeddable in a large-area electronic system.
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solution processed zinc indium oxide transparent Nonvolatile Memory thin film transistors with polymeric ferroelectric gate insulator
Electrochemical and Solid State Letters, 2010Co-Authors: Sung Min Yoon, Shin Hyuk Yang, Chun Won Byun, Soon-won Jung, Chi-sun Hwang, Sanghee Ko Park, Hiroshi IshiwaraAbstract:Solution-Processed Zinc Indium Oxide Transparent Nonvolatile Memory Thin-Film Transistors with Polymeric Ferroelectric Gate Insulator Sung-Min Yoon, Shin-Hyuk Yang, Soon-Won Jung, Chun-Won Byun, Sang-Hee Ko Park, Chi-Sun Hwang, and Hiroshi Ishiwara* Tokyo Institute of Technology, Yokohama 226-8502, Japan Convergence Components and Material Research Laboratory, Electronics and Telecommunications Research Institute, Daejeon 305-700, Korea
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Effect of ZnO channel thickness on the device behaviour of Nonvolatile Memory thin film transistors with double-layered gate insulators of Al 2O3 and ferroelectric polymer
Journal of Physics D: Applied Physics, 2009Co-Authors: Sung Min Yoon, Shin Hyuk Yang, Chun Won Byun, Doo Hee Cho, Soon-won Jung, Chi-sun Hwang, Seung Youl Kang, Sang Hee Park, Byoung Gon YuAbstract:Poly(vinylidene fluoride trifluoroethylene) and ZnO were employed for Nonvolatile Memory thin film transistors as ferroelectric gate insulator and oxide semiconducting channel layers, respectively. It was proposed that the thickness of the ZnO layer be carefully controlled for realizing the lower programming voltage, because the serially connected capacitor by the formation of a fully depleted ZnO channel had a critical effect on the off programming voltage. The fabricated Memory transistor with Al/P(VDF-TrFE) (80 nm)/Al 2 O 3 (4 nm)/ZnO (5 nm) exhibits encouraging behaviour such as a Memory window of 3.8 V at the gate voltage of -10 to 12 V, and 10 7 on/off ratio, and a gate leakage current of 10 -11 A. © 2009 IOP Publishing Ltd.
Yang Yang - One of the best experts on this subject based on the ideXlab platform.
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modulating the filament rupture degree of threshold switching device for self selective and low current Nonvolatile Memory application
Nanotechnology, 2020Co-Authors: Yang Yang, Shibing Long, Xiaolong Zhao, Jiebin Niu, Xiangheng Xiao, Rui Chen, Ying Zhang, Qi Liu, Changzhong JiangAbstract:Resistive switching devices have tremendous potential for Memory, logic, and neuromorphic computing applications. Cation-based resistive switching devices intrinsically show Nonvolatile Memory characteristics under high compliance current (I CC), while show volatile threshold switching (TS) selector characteristics under low I CC. However, separate researches about cation-based Memory or selector are hard to evade the typical current-retention dilemma, which results in the hardship to obtain low-current Memory and high-current selector. Here, we propose a novel strategy to realize Nonvolatile storage characteristics in a volatile TS device by modulating the rupture degree of conductive filament (CF). Enlarging the rupture degree of the CF with a certain RESET process, as confirmed by transmission electron microscope and energy dispersive spectrometry results, the threshold voltage of the Ag/HfO2/Pt TS devices can be enlarged from 0.9 to 2.8 V. Generation of the voltage difference enables the volatile TS devices the ability of self-selective Nonvolatile storage. Increasing the RESET magnitude and shrinking the device size have been proved effective ways to increase the read window of the TS Memory (TSM) devices. Evading the limit of the current-retention dilemma, ultra-low energy dissipation can be obtained by decreasing I CC to nA level. With self-selective, low-energy, and potential high-density integration characteristics, the proposed TSM device can act as a potential supplement of novel storage class memories.
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polymer metal nanoparticle devices with electrode sensitive bipolar resistive switchings and their application as Nonvolatile Memory devices
Applied Physics Letters, 2010Co-Authors: Jianyong Ouyang, Yang YangAbstract:Devices with a polystyrene film blended with gold nanoparticles capped with conjugated 2-naphthalenethiol exhibited electrode-sensitive bipolar resistive switchings. The resistances of the two states could be different by almost three orders of magnitude, and the devices could be switched between the two states for numerous times. Thus, these devices can be used as Nonvolatile Memory devices. The resistive switching voltage is related to the work function of the electrode. The electrode sensitivity of the resistive switchings is attributed to the contact potential at the contact of gold nanoparticles and electrode arising from charge transfer between them.
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organic Nonvolatile Memory by controlling the dynamic copper ion concentration within organic layer
Applied Physics Letters, 2004Co-Authors: Qianfei Xu, Yang YangAbstract:Copper (Cu) migration into semiconductor materials like silicon is a well-known and troublesome phenomenon often causing adverse effect on devices. Generally a diffusion barrier layer is added to prevent Cu metallization. We demonstrate an organic Nonvolatile Memory device by controlling the Cu-ion (Cu+) concentration within the organic layer. When the Cu+ concentration is high enough, the device exhibits a high conductive state due to the metallization effect. When the Cu+ concentration is low, the device displays a low conductance state. These two states differ in their electrical conductivity by more than seven orders of magnitude and can be precisely switched by controlling the Cu+ concentration through the application of external biases. The retention time of both states can be more than several months, and the device is promising for flash Memory application. Discussions about the device operation mechanism are provided.
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charge retention of scaled sonos Nonvolatile Memory devices at elevated temperatures
Solid-state Electronics, 2000Co-Authors: Yang Yang, M H WhiteAbstract:Abstract The charge retention characteristics in scaled SONOS Nonvolatile Memory devices with an effective gate oxide thickness of 94 A and a tunnel oxide of 15 A are investigated in a temperature range from room temperature to 175°C. Electron charge decay rate is sensitive to the temperature, whereas hole charge decay rate remains essentially constant. Based on experimental observations and an amphoteric trap model for nitride traps, an analytical model for charge retention of the excess electron state is developed. Using this thermal activated electron retention model, the trap distribution in energy within the nitride film is extracted.
Hyunsang Hwang - One of the best experts on this subject based on the ideXlab platform.
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hpha effect on reversible resistive switching of pt nb doped srtio3 schottky junction for Nonvolatile Memory application
Electrochemical and Solid State Letters, 2007Co-Authors: Dongjun Seong, Dongsoo Lee, Hyunsang HwangAbstract:We investigated the effect of high-pressure hydrogen annealing (HPHA) on a Pt/Nb-doped SrTiO 3 Schottky junction for Nonvolatile Memory applications. Hysteretic current-voltage (I-V) characteristic curves reveal that the HPHA-treated Schottky junction interface has a higher resistance ratio than the control sample in dc bias sweep. The HPHA sample also exhibits switching behavior by pulsed voltage stress with excellent electrical characteristics including voltage pulse duration as short as 1 μs, endurance cycles of up to 10 6 times, and retention time as long as 10 5 s. These indicate that HPHA improved resistance switching characteristics of the Schottky junction.
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Memory characteristics of silicon nitride with silicon nanocrystals as a charge trapping layer of Nonvolatile Memory devices
Applied Physics Letters, 2005Co-Authors: Sangmoo Choi, Hyundeok Yang, Man Chang, Sungkweon Baek, Hyunsang Hwang, Sanghun Jeon, Juhyung Kim, Chungwoo KimAbstract:Silicon nitride with silicon nanocrystals formed by low-energy silicon plasma immersion ion implantation has been investigated as a charge trapping layer of a polycrystalline silicon-oxide-nitride-oxide-silicon-type Nonvolatile Memory device. Compared with the control sample without silicon nanocrystals, silicon nitride with silicon nanocrystals provides excellent Memory characteristics, such as larger width of capacitance-voltage hysteresis, higher program∕erase speed, and lower charge loss rate at elevated temperature. These improved Memory characteristics are derived by incorporation of silicon nanocrystals into the charge trapping layer as additional accessible charge traps with a deeper effective trap energy level.
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resistance switching characteristics of polycrystalline nb sub 2 o sub 5 for Nonvolatile Memory application
IEEE Electron Device Letters, 2005Co-Authors: Hyunjun Sim, Dooho Choi, Dongsoo Lee, Sunae Seo, Myongjae Lee, Inkyeong Yoo, Hyunsang HwangAbstract:The resistance switching characteristics of polycrystalline Nb/sub 2/O/sub 5/ film prepared by pulsed-laser deposition (PLD) were investigated for Nonvolatile Memory application. Reversible resistance-switching behavior from a high resistance state to a lower state was observed by voltage stress with current compliance. The reproducible resistance-switching cycles were observed and the resistance ratio was as high as 50-100 times. The resistance switching was observed under voltage pulse as short as 10 ns. The estimated retention lifetime at 85/spl deg/C was sufficiently longer than ten years. Considering its excellent electrical and reliability characteristics, Nb/sub 2/O/sub 5/ shows strong promise for future Nonvolatile Memory applications.
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Resistance switching of the nonstoichiometric zirconium oxide for Nonvolatile Memory applications
IEEE Electron Device Letters, 2005Co-Authors: Hyejung Choi, Dooho Choi, Hyunsang HwangAbstract:The resistance switching behavior and switching mechanism of nonstoichiometric zirconium oxide thin films were investigated for Nonvolatile Memory application. The Pt/ZrO/sub x//p/sup +/-Si sandwich structure fabricated by reactive sputtering shows two stable resistance states. By applying proper bias, resistance switching from one to another state can be obtained. The composition in ZrO/sub x/ thin films were confirmed from X-ray photoelectron spectroscope (XPS) analysis, which showed three layers such as top stoichiometric ZrO/sub 2/ layer with high resistance, transition region with medium resistance, and conducting ZrO/sub x/ bulk layer. The resistance switching can be explained by electron trapping and detrapping of excess Zr/sup +/ ions in transition layer which control the distribution of electric field inside the oxide, and, hence the current flow.
Seunghyup Yoo - One of the best experts on this subject based on the ideXlab platform.
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Nonvolatile Memory based on sol gel zno thin film transistors with ag nanoparticles embedded in the zno gate insulator interface
Applied Physics Letters, 2008Co-Authors: Dipti Gupta, Manish Anand, Seongwan Ryu, Yangkyu Choi, Seunghyup YooAbstract:A Nonvolatile Memory is demonstrated using a solution-processed sol-gel ZnO thin-film transistor (TFT) in which Ag nanoparticles are embedded as charge storage nodes at the insulator-ZnO interface. Its TFT transfer characteristics exhibit a large clockwise hysteresis that is proportional to the gate bias sweep range. Measurement of the threshold voltage shift versus the pulse width of gate bias reveals that the device can be programed or erased at a time scale of as short as 10−4 s. Retention of the initial Memory window is measured to be 27% after 105 s and projected to last until 107 s.
Chi-sun Hwang - One of the best experts on this subject based on the ideXlab platform.
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effects of thickness and geometric variations in the oxide gate stack on the Nonvolatile Memory behaviors of charge trap Memory thin film transistors
Solid-state Electronics, 2015Co-Authors: Jun Yong Bak, Chun Won Byun, Chi-sun Hwang, Minki Ryu, Sojung Kim, Sung Min YoonAbstract:Abstract Device designs of charge-trap oxide Memory thin-film transistors (CTM-TFTs) were investigated to enhance their Nonvolatile Memory performances. The first strategy was to optimize the film thicknesses of the tunneling and charge-trap (CT) layers in order to meet requirements of both higher operation speed and longer retention time. While the program speed and Memory window were improved for the device with a thinner tunneling layer, a long retention time was obtained only for the device with a tunneling layer thicker than 5 nm. The carrier concentration and charge-trap densities were optimized in the 30-nm-thick CT layer. It was observed that 10-nm-thick tunneling, 30-nm-thick CT, and 50-nm-thick blocking layers were the best configuration for our proposed CTM-TFTs, where a Memory on/off margin higher than 10 7 was obtained, and a Memory margin of 6.6 × 10 3 was retained even after the lapse of 10 5 s. The second strategy was to examine the effects of the geometrical relations between the CT and active layers for the applications of Memory elements embedded in circuitries. The CTM-TFTs fabricated without an overlap between the CT layer and the drain electrode showed an enhanced program speed by the reduced parasitic capacitance. The drain-bias disturbance for the Memory off-state was effectively suppressed even when a higher read-out drain voltage was applied. Appropriate device design parameters, such as the film thicknesses of each component layer and the geometrical relations between them, can improve the Memory performances and expand the application fields of the proposed CTM-TFTs.
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oxide semiconductor based organic inorganic hybrid dual gate Nonvolatile Memory thin film transistor
IEEE Transactions on Electron Devices, 2011Co-Authors: Sung Min Yoon, Shin Hyuk Yang, Chun Won Byun, Soon-won Jung, Chi-sun Hwang, Sanghee Ko Park, Minki Ryu, Kyoungik ChoAbstract:An organic/inorganic hybrid dual-gate (DG) Nonvolatile Memory thin-film transistor (M-TFT) was proposed as a device with high potential for implementing large-area electronics on flexible and/or transparent substrates. The active channel and bottom and top gate insulators (GIs) of the M-TFT were composed of In-Ga-Zn-O, Al2O3, and poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)], respectively. It was confirmed that the fabricated DG M-TFT showed excellent device characteristics, in which the obtained field-effect mobility, subthreshold swing, and on/off ratio were approximately 32.1 cm2 V-1 s-1, 0.13 V/dec, and 108, respectively. It was also successfully demonstrated that the DG configuration for the proposed M-TFT could effectively work for improving the device controllability by individually controlling the bias conditions of the top gate and bottom gate (BG). The turn-on voltage could be dynamically modulated and controlled when an appropriate fixed negative voltage was applied to the BG. The required duration of the programming pulse to obtain a Memory margin of more than 10 could be reduced to 100 μs. These results correspond to the first demonstration of a hybrid-type DG M-TFT using a ferroelectric copolymer GI/oxide semiconducting active channel structure and demonstrate the feasibility of a promising Memory device embeddable in a large-area electronic system.
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solution processed zinc indium oxide transparent Nonvolatile Memory thin film transistors with polymeric ferroelectric gate insulator
Electrochemical and Solid State Letters, 2010Co-Authors: Sung Min Yoon, Shin Hyuk Yang, Chun Won Byun, Soon-won Jung, Chi-sun Hwang, Sanghee Ko Park, Hiroshi IshiwaraAbstract:Solution-Processed Zinc Indium Oxide Transparent Nonvolatile Memory Thin-Film Transistors with Polymeric Ferroelectric Gate Insulator Sung-Min Yoon, Shin-Hyuk Yang, Soon-Won Jung, Chun-Won Byun, Sang-Hee Ko Park, Chi-Sun Hwang, and Hiroshi Ishiwara* Tokyo Institute of Technology, Yokohama 226-8502, Japan Convergence Components and Material Research Laboratory, Electronics and Telecommunications Research Institute, Daejeon 305-700, Korea
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Effect of ZnO channel thickness on the device behaviour of Nonvolatile Memory thin film transistors with double-layered gate insulators of Al 2O3 and ferroelectric polymer
Journal of Physics D: Applied Physics, 2009Co-Authors: Sung Min Yoon, Shin Hyuk Yang, Chun Won Byun, Doo Hee Cho, Soon-won Jung, Chi-sun Hwang, Seung Youl Kang, Sang Hee Park, Byoung Gon YuAbstract:Poly(vinylidene fluoride trifluoroethylene) and ZnO were employed for Nonvolatile Memory thin film transistors as ferroelectric gate insulator and oxide semiconducting channel layers, respectively. It was proposed that the thickness of the ZnO layer be carefully controlled for realizing the lower programming voltage, because the serially connected capacitor by the formation of a fully depleted ZnO channel had a critical effect on the off programming voltage. The fabricated Memory transistor with Al/P(VDF-TrFE) (80 nm)/Al 2 O 3 (4 nm)/ZnO (5 nm) exhibits encouraging behaviour such as a Memory window of 3.8 V at the gate voltage of -10 to 12 V, and 10 7 on/off ratio, and a gate leakage current of 10 -11 A. © 2009 IOP Publishing Ltd.
