The Experts below are selected from a list of 747 Experts worldwide ranked by ideXlab platform
Ya-chin King - One of the best experts on this subject based on the ideXlab platform.
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Antifuse OTP Cell in a Cross-Point Array by Advanced CMOS FinFET Process
IEEE Transactions on Electron Devices, 2019Co-Authors: Fu-cheng Chang, Ya-chin KingAbstract:A new antifuse one-time programmable (OTP) memory array by the 16-nm FinFET high-κ metal gate process is proposed and demonstrated. The OTP cells are programed by gate dielectric breakdown. The asymmetric I-V characteristics can be achieved by controlling the current compliance level during its programming operation. Based on the diode-like postbreakdown I-V characteristics, a high-density cross-point array without cell selectors is demonstrated, by the advanced FinFET CMOS technology.
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Variable-length gateless transistor for analog one-time-programmable memory applications
2016 International Symposium on VLSI Technology Systems and Application (VLSI-TSA), 2016Co-Authors: Po-ruei Cheng, Chih-sung Yang, Ya-chin KingAbstract:This work presents a novel embedded Analog Gateless one-time-Programming Memory (AG-OTP), implemented by standard CMOS logic process. The NVM cell includes a gateless storage node in series with a select transistor; where the charge stored on the parasitic ONO structure. The p-channel device is programmed by channel hot hole induced hot electron injection (CHHIHE). An angled-shaped source region allows the gateless channel to be partially turned-on and gradually increase the read current level. This unique structure enable the storage of analog data as continuous read current can be readily achieved.
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A high density FinFET one-time programmable cell with new intra-fin cell isolation for advanced system on chip applications
Japanese Journal of Applied Physics, 2016Co-Authors: Yu-zheng Chen, Ping Chun Peng, Woan Yun Hsiao, Jo En Yuan, Ya-chin KingAbstract:A fully CMOS compatible one-time programmable (OTP) cell with a novel intra-fin cell isolation (IFCI) structure on a FinFET CMOS process has been proposed. The IFCI OTP cell utilizes the field-enhanced dielectric breakdown at fin corners to perform a fast and low-voltage program operation. Moreover, an ultrasmall intra-fin cell-to-cell isolation is firstly introduced to markedly shrink the cell size by eliminating the area-consuming spacing of fin-to-fin isolation. The IFCI FinFET OTP with fast program speed, excellent read disturb immunity, and reliable data retention is a promising solution for logic nonvolatile memory (NVM) technology in advanced CMOS nodes.
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Multilevel Anti-Fuse Cells by Progressive Rupturing of the High- $\kappa $ Gate Dielectric in FinFET Technologies
IEEE Electron Device Letters, 2016Co-Authors: Yu-zheng Chen, Jo En Yuan, Ya-chin KingAbstract:A new operation scheme is proposed for achieving multilevel storage in FinFET one-time programmable (OTP) cells by a high-κ metal gate CMOS process. The OTP cells are programmed by breaking down the gate dielectric layer, during which the corner effect in the FinFET structure shortens the program time and lowers the program voltages. The after-breakdown resistance in the storage node is found to be well-controlled by the compliance current level set by the select transistor. By using WL voltage control, the multilevel OTP cell with superior data retention and disturb immunity is successfully used in advanced logic nonvolatile memory applications.
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High-Density FinFET one-time programmable Memory Cell With Intra-Fin-Cell-Isolation Technology
IEEE Electron Device Letters, 2015Co-Authors: Ping Chun Peng, Yu-zheng Chen, Woan Yun Hsiao, Kuang-hsin Chen, Bor-zen Tien, Tzong-sheng Chang, Ya-chin KingAbstract:The one-time programmable (OTP) cell with intra-Fin-cell-isolation (IFCI) on the FinFET high-k metal gate (HKMG) CMOS process is proposed and demonstrated. The field-enhanced dielectric breakdown at Fin corners enables this OTP cell to be operated at low program voltage with fast program speed. The new intra-Fin cell-to-cell isolation eliminates the required wide spacing in the conventional isolation schemes, which successfully shields the neighboring cells from program and read disturbs. Without introducing extra masks or process steps, the CMOS compatible IFCI OTP cell achieves an ultrasmall cell size of 0.076 $\mu \text{m}^{2}$ . More than six orders of ON-/OFF-read window is achieved under 4 V programming within 20 $\mu \text{s}$ .
Mansun Chan - One of the best experts on this subject based on the ideXlab platform.
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one-time-programmable Memory in LTPS TFT Technology With Metal-Induced Lateral Crystallization
IEEE Transactions on Electron Devices, 2012Co-Authors: Lin Li, Chi On Chui, Jin He, Mansun ChanAbstract:A simple and reliable one-time-programmable (OTP) memory for low-temperature polysilicon thin-film-transistor technology with metal-induced lateral crystallization (MILC) is developed. The antifuse memory element is based on the breakdown of thin silicon dioxide deposited on smooth surface achieved by MILC. The effects of crystallization process and electrode configurations on the memory characteristics, including statistical variations, are studied. A read current margin of 106 is achieved for the fresh and programmed memory element. Functional OTP memory array with compact layout and high disturb immunity using a split supply configuration is also demonstrated.
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Diode based gate oxide anti-fuse one time programmable memory array in standard CMOS process
2009 IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC), 2009Co-Authors: K. P. Ng, K. C. Kwong, Mansun ChanAbstract:A diode based gate oxide anti-fuse one time programmable memory array in standard CMOS process without additional process is presented. The requirements of various components in the anti-fuse cell are discussed. The solution to high voltage reliability problem when programming the gate oxide anti-fuse is provided. Measurement results are performed to confirm the functionality of the design.
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CMOS-compatible zero-mask One Time programmable (OTP) memory design
2008 9th International Conference on Solid-State and Integrated-Circuit Technology, 2008Co-Authors: Wan Tim Chan, K. P. Ng, K. C. Kwong, Lin Li, Ricky M. Y. Ng, Mansun ChanAbstract:A method to design CMOS-compatible diode-based one-time programmable (OTP) memory is discussed in this paper. In particular the program disturb problem is resolved by using diode drivers with sufficiently high breakdown voltage. The choices of memory elements and various available diodes in a standard CMOS process are carefully studied to obtain an optimal combination. Different memory cells were fabricated in standard 0.18-¿m CMOS technology to verify the functionality of the design.
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Universal high voltage multiplexer for CMOS OTP memory applications
2008 IEEE International Conference on Electron Devices and Solid-State Circuits, 2008Co-Authors: Kwok Ping Ng, Wan Tim Chan, Randy Barsatan, Mansun ChanAbstract:A CMOS-compatible high voltage multiplexer (HV MUX) for zero-additional-mask CMOS one time programmable (OTP) memory array mask is presented. The HV MUX uses standard CMOS with low input voltage and produce high output voltage beyond the VDD allowed by the process for programming the OTP memory array. By limiting the instantaneous voltage between any two nodes, the HV MUX can tolerate the high voltages for programming without sacrificing reliability. Two configurations of CMOS OTP memory array using the HV MUX are presented and simulated to confirm the functionality of the design.
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OTP Memory for Low Cost Passive RFID Tags
2007 IEEE Conference on Electron Devices and Solid-State Circuits, 2007Co-Authors: Randy Barsatan, Mansun ChanAbstract:A CMOS-compatible zero-additional- mask one time programmable (OTP) non-volatile memory (NVM) for passive radio frequency identification (RFID) tags is presented. The selection of anti-fuse (AF) elements is discussed. The high voltage (HV) reliability issue for AF arrays is investigated and a high voltage switch drawing zero DC current is developed to tolerate the high voltages required for programming. Various AF memory cells and the HV switch were fabricated in standard TSMC 0.18 μm process. The breakdown of the AFs has been characterized and the functionality of the HV switch has been verified by measurement.
Ik Joon Chang - One of the best experts on this subject based on the ideXlab platform.
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A 2-Kb one-time programmable Memory for UHF Passive RFID Tag IC in a Standard 0.18 $\mu$ m CMOS Process
IEEE Transactions on Circuits and Systems, 2013Co-Authors: Ngoc Dang Phan, Ik Joon ChangAbstract:We present a 2-Kb one-time programmable (OTP) memory for UHF RFID applications. The OTP memory cell is based on a two-transistor (2-T) gate-oxide anti-fuse (AF) for low voltage operation. Reliability of memory cell is enhanced by limiting the maximum terminal voltages of thin-oxide and thick-oxide transistors to 1.8 V and 3.3 V, respectively. Improved low power circuit design techniques are used including auto shut-off for program mode and self-timed control for read mode. To further reduce power consumption, we develop a novel power-efficient charge pump. The designed OTP is successfully embedded into a UHF passive RFID tag IC that conforms to the EPCglobal Gen-2 standard. The tag chip was fabricated in a 0.18 m 1-poly 6-metal standard CMOS process with no additional masks. The total area of the chip including the I/Os and bonding pads is 2.3 × 1.5 mm2 where the OTP memory area is only 0.43 × 0.31 mm2. Our tag IC measurement shows that the read and write currents of the OTP memory are 17 μA and 58 μA, respectively.
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A 2-Kb one-time programmable Memory for UHF Passive RFID Tag IC in a Standard 0.18 /spl mu/m CMOS Process
IEEE Transactions on Circuits and Systems I: Regular Papers, 2013Co-Authors: Ngoc Dang Phan, Ik Joon ChangAbstract:We present a 2-Kb one-time programmable (OTP) memory for UHF RFID applications. The OTP memory cell is based on a two-transistor (2-T) gate-oxide anti-fuse (AF) for low voltage operation. Reliability of memory cell is enhanced by limiting the maximum terminal voltages of thin-oxide and thick-oxide transistors to 1.8 V and 3.3 V, respectively. Improved low power circuit design techniques are used including auto shut-off for program mode and self-timed control for read mode. To further reduce power consumption, we develop a novel power-efficient charge pump. The designed OTP is successfully embedded into a UHF passive RFID tag IC that conforms to the EPCglobal Gen-2 standard. The tag chip was fabricated in a 0.18 m 1-poly 6-metal standard CMOS process with no additional masks. The total area of the chip including the I/Os and bonding pads is 2.3 × 1.5 mm2 where the OTP memory area is only 0.43 × 0.31 mm2. Our tag IC measurement shows that the read and write currents of the OTP memory are 17 μA and 58 μA, respectively.
Ngoc Dang Phan - One of the best experts on this subject based on the ideXlab platform.
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A 2-Kb one-time programmable Memory for UHF Passive RFID Tag IC in a Standard 0.18 $\mu$ m CMOS Process
IEEE Transactions on Circuits and Systems, 2013Co-Authors: Ngoc Dang Phan, Ik Joon ChangAbstract:We present a 2-Kb one-time programmable (OTP) memory for UHF RFID applications. The OTP memory cell is based on a two-transistor (2-T) gate-oxide anti-fuse (AF) for low voltage operation. Reliability of memory cell is enhanced by limiting the maximum terminal voltages of thin-oxide and thick-oxide transistors to 1.8 V and 3.3 V, respectively. Improved low power circuit design techniques are used including auto shut-off for program mode and self-timed control for read mode. To further reduce power consumption, we develop a novel power-efficient charge pump. The designed OTP is successfully embedded into a UHF passive RFID tag IC that conforms to the EPCglobal Gen-2 standard. The tag chip was fabricated in a 0.18 m 1-poly 6-metal standard CMOS process with no additional masks. The total area of the chip including the I/Os and bonding pads is 2.3 × 1.5 mm2 where the OTP memory area is only 0.43 × 0.31 mm2. Our tag IC measurement shows that the read and write currents of the OTP memory are 17 μA and 58 μA, respectively.
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A fully integrated UHF passive tag IC having one-time programmable memory in standard CMOS technology
2013 International SoC Design Conference (ISOCC), 2013Co-Authors: Vinh Hao Duong, Ngoc Dang Phan, Dasom ParkAbstract:We present a 2-Kb one-time programmable (OTP) memory for high security RFID applications. The OTP memory cell is based on a two-transistor (2-T) gate-oxide anti-fuse (AF) for low voltage operation. Improved low power circuit design techniques are used including auto shut-off for program mode and self-timed control for read mode. The designed OTP is successfully embedded into a UHF passive RFID tag IC that conforms to the EPCglobal Gen-2 standard. The tag chip was fabricated in a 0.18 μm 1-poly 6-metal standard CMOS process with no additional masks.
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A 2-Kb one-time programmable Memory for UHF Passive RFID Tag IC in a Standard 0.18 /spl mu/m CMOS Process
IEEE Transactions on Circuits and Systems I: Regular Papers, 2013Co-Authors: Ngoc Dang Phan, Ik Joon ChangAbstract:We present a 2-Kb one-time programmable (OTP) memory for UHF RFID applications. The OTP memory cell is based on a two-transistor (2-T) gate-oxide anti-fuse (AF) for low voltage operation. Reliability of memory cell is enhanced by limiting the maximum terminal voltages of thin-oxide and thick-oxide transistors to 1.8 V and 3.3 V, respectively. Improved low power circuit design techniques are used including auto shut-off for program mode and self-timed control for read mode. To further reduce power consumption, we develop a novel power-efficient charge pump. The designed OTP is successfully embedded into a UHF passive RFID tag IC that conforms to the EPCglobal Gen-2 standard. The tag chip was fabricated in a 0.18 m 1-poly 6-metal standard CMOS process with no additional masks. The total area of the chip including the I/Os and bonding pads is 2.3 × 1.5 mm2 where the OTP memory area is only 0.43 × 0.31 mm2. Our tag IC measurement shows that the read and write currents of the OTP memory are 17 μA and 58 μA, respectively.
Jin He - One of the best experts on this subject based on the ideXlab platform.
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one-time-programmable Memory in LTPS TFT Technology With Metal-Induced Lateral Crystallization
IEEE Transactions on Electron Devices, 2012Co-Authors: Lin Li, Chi On Chui, Jin He, Mansun ChanAbstract:A simple and reliable one-time-programmable (OTP) memory for low-temperature polysilicon thin-film-transistor technology with metal-induced lateral crystallization (MILC) is developed. The antifuse memory element is based on the breakdown of thin silicon dioxide deposited on smooth surface achieved by MILC. The effects of crystallization process and electrode configurations on the memory characteristics, including statistical variations, are studied. A read current margin of 106 is achieved for the fresh and programmed memory element. Functional OTP memory array with compact layout and high disturb immunity using a split supply configuration is also demonstrated.
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A Compact CMOS Compatible Oxide Antifuse With Polysilicon Diode Driver
IEEE Transactions on Electron Devices, 2012Co-Authors: Jin He, Wan Tim Chan, Lin Li, Ruonan Wang, Wen Wu, Cheng Wang, Hailang Liang, Yun Ye, Qin Chen, Xiaomeng HeAbstract:A very compact one-time-programmable memory consisting of an oxide antifuse and a polysilicon diode driver is proposed in this brief. The memory cell is constructed using a standard CMOS process without any additional masks to reduce the fabrication cost. The design method to achieve the required performance of various components is presented in detail. The technology has been demonstrated with a fabricated chip from a standard 0.18- $\mu\hbox{m}$ CMOS TSMC technology.
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Zero-Mask Contact Fuse for one-time-programmable Memory in Standard CMOS Processes
IEEE Electron Device Letters, 2011Co-Authors: Min Shi, Jin He, Lining Zhang, Xingye Zhou, Haijun Lou, Hao Zhuang, Ruonan Wang, Yongliang Li, Wen Wu, Wenping WangAbstract:This letter describes the formation of one-time-programmable (OTP) memory using standard contact fuse and polysilicon diode in a standard CMOS technology. Programming of the contact fuse is achieved by applying a high current pulse to destroy the contact. Compared with other existing OTP technologies, the proposed approach has the advantage of zero additional mask, no additional processing step, compact structure, and low programming voltage. The described OTP has been demonstrated in a 0.18-μm CMOS technology from TSMC with a cell size of 2.33 μm2 . The contact fuse can be programmed with a voltage of 3 V and a current of 2.4 mA.
