The Experts below are selected from a list of 76593 Experts worldwide ranked by ideXlab platform

Kunhsien Lin - One of the best experts on this subject based on the ideXlab platform.

  • the impact of low holding Voltage issue in high Voltage cmos technology and the design of latchup free Power rail esd clamp circuit for lcd driver ics
    IEEE Journal of Solid-state Circuits, 2005
    Co-Authors: Kunhsien Lin
    Abstract:

    The holding Voltage of the high-Voltage devices in snapback breakdown condition has been found to be much smaller than the Power Supply Voltage. Such characteristics will cause the LCD driver ICs to be susceptible to the latchup-like danger in the practical system applications, especially while these devices are used in the Power-rail ESD clamp circuit. A new latchup-free design on the Power-rail ESD clamp circuit with stacked-field-oxide structure is proposed and successfully verified in a 0.25-/spl mu/m 40-V CMOS process to achieve the desired ESD level. The total holding Voltage of the stacked-field-oxide structure in snapback breakdown condition can be larger than the Power Supply Voltage. Therefore, latchup or latchup-like issues can be avoided by stacked-field-oxide structures for the IC applications with Power Supply of 40 V.

  • design on latchup free Power rail esd clamp circuit in high Voltage cmos ics
    Electrical Overstress Electrostatic Discharge Symposium, 2004
    Co-Authors: Kunhsien Lin
    Abstract:

    The holding Voltage of the high-Voltage ESD protection devices in snapback breakdown condition has been found to be much smaller than the Power Supply Voltage. Such characteristics will cause the high-Voltage CMOS ICs susceptible to the latchup-like danger in the real system applications, especially while these devices are used in the Power-rail ESD clamp circuit. A new latchup-free design on the Power-rail ESD clamp circuit with stacked-field-oxide structure is proposed and successfully verified in a 0.25-mum 40-V CMOS process to achieve the desired ESD level. The total holding Voltage of the stacked-field-oxide structure in snapback breakdown condition can be larger than the Power Supply Voltage. Therefore, latchup or latchup-like issues can be avoided by stacked-field-oxide structures for the IC applications with VDD of 40 V.

  • double snapback characteristics in high Voltage nmosfets and the impact to on chip esd protection design
    IEEE Electron Device Letters, 2004
    Co-Authors: Kunhsien Lin
    Abstract:

    The double snapback characteristic in the high-Voltage nMOSFET under transmission line pulsing stress is found. The physical mechanism of double snapback phenomenon in the high-Voltage nMOSFET is investigated by device simulation. With double snapback characteristic in high-Voltage nMOSFET, the holding Voltage of the high-Voltage nMOSFET in snapback breakdown condition has been found to be much smaller than the Power Supply Voltage. Such characteristic will cause the high-Voltage CMOS ICs susceptible to the latchup-like danger in the real system applications, especially while the high-Voltage nMOSFET is used in the Power-rail electrostatic discharge clamp circuit.

A P Dorey - One of the best experts on this subject based on the ideXlab platform.

  • testing analogue circuits by ac Power Supply Voltage
    International Conference on VLSI Design, 1996
    Co-Authors: Abu Khari Bin Aain, A H Bratt, A P Dorey
    Abstract:

    This paper discusses the application of Power Supply Voltage control testing technique for analogue circuits. It compares the fault coverage of Voltage level and Supply current monitoring schemes and proposes a technique to expose defects in redundant circuits that are very difficult to expose using other testing techniques. It also discusses the effect in exposing defects by using different Power Supply frequency. Measurement and data analysis techniques to facilitate identification and classification between hard and soft defects is also proposed.

  • on the development of Power Supply Voltage control testing technique for analogue circuits
    Asian Test Symposium, 1995
    Co-Authors: Abu Khari Bin Aain, A H Bratt, A P Dorey
    Abstract:

    This paper discusses a novel testing technique for analogue circuits. The theory behind its success in exposing defects normally unexposed by other testing techniques is presented. This is supported by simulation results and real IC tests. Due to its modest requirement to perform the test, this testing scheme is more attractive and beneficial. Methods of data analysis are also proposed to expose hard and soft defects. The advantages of the proposed testing scheme are fast to implement, uses simple test vector and does not require additional test circuitry on-chip.

  • exposing floating gate defects in analogue cmos circuits by Power Supply Voltage control testing technique
    International Conference on VLSI Design, 1995
    Co-Authors: Abu Khari Bin Aain, A H Bratt, A P Dorey
    Abstract:

    In this paper a novel development of a testing technique for analogue integrated circuits based on sweeping the Power Supply Voltage is described. It is shown that by using a simple floating gate fault model together with the proposed scheme it is possible to achieve a high fault coverage. The scope of work discussed in this paper is focused on exposing floating gate defects which, using other methods, usually requires careful and accurate knowledge of the elements, including parasitic components, of the equivalent circuit of the devices.

  • testing analogue circuits by Power Supply Voltage control
    Electronics Letters, 1994
    Co-Authors: Abu Khari Bin Aain, A H Bratt, A P Dorey
    Abstract:

    By varying the Power Supply Voltages of an analogue integrated circuit as a testing technique it is possible to expose faults within the circuits which are difficult to detect by conventional input Voltage stimulation. This technique is simple to implement and does not incur any area overhead penalty.

Michiel Steyaert - One of the best experts on this subject based on the ideXlab platform.

  • a 1 75 ghz 3 v dual modulus divide by 128 129 prescaler in 0 7 spl mu m cmos
    IEEE Journal of Solid-state Circuits, 1996
    Co-Authors: Jan Craninckx, Michiel Steyaert
    Abstract:

    A dual-modulus divide-by-128/129 prescaler has been developed in a 0.7-/spl mu/m CMOS technology. A new circuit technique enables the limitation of the high-speed section of the prescaler to only one divide-by-two flipflop. In that way, a dual-modulus prescaler with the same speed as an asynchronous divider can be obtained. The measured maximum input frequency of the prescaler is up to 2.65 GHz at 5 V Power Supply Voltage. Running at a Power Supply of 3 V, the circuit consumes 8 mA at a minimum input frequency of 1.75 GHz.

Taihua Chen - One of the best experts on this subject based on the ideXlab platform.

  • an ultra low Power memory with a subthreshold Power Supply Voltage
    IEEE Journal of Solid-state Circuits, 2006
    Co-Authors: Jinhui Chen, Lawrence T Clark, Taihua Chen
    Abstract:

    A 512times13 bit ultra-low-Power subthreshold memory is fabricated on a 130-nm process technology. The fabricated memory is fully functional for read operation with a 190-mV Power Supply at 28 kHz, and 216 mV for write operation. Single bits are measured to read and write properly with VDD as low as 103 mV and 129 mV, respectively. The memory operates at a 1-MHz clock rate with a 310-mV Power Supply. This operating point has 1.197 muW Power consumption, of which 0.366 muW is due to leakage and 0.831 muW is due to dynamic Power dissipation. Analysis of the available fan-out or fan-in that can be supported at a given Voltage is summarized. A number of circuit techniques are presented to overcome the substantially reduced on-to-off current ratios and the poor drive strength of transistors operating in subthreshold. These include a gated feedback memory cell, and hierarchical read and decode circuits. The memory is dynamic, with pseudo-static operation provided via self-timed control of the keeper transistors to mitigate increased variability manifested in subthreshold operation

Apinunt Thanachayanont - One of the best experts on this subject based on the ideXlab platform.

  • A 1-V, 6-nW programmable 4th-order bandpass filter for biomedical applications
    Analog Integrated Circuits and Signal Processing, 2016
    Co-Authors: Yuwadee Sundarasaradula, Apinunt Thanachayanont
    Abstract:

    This paper describes the design and realization of a programmable 4th-order, G_m-C bandpass filter for biomedical applications. The core 2nd-order filter stage is realized by a simple gyrator-C active inductor structure with a single MOSFET as the transconductor element. The capacitive input attenuation technique is used to enhance the linearity of the filter. The proposed filter was designed and simulated with a 1-V Power Supply Voltage with process parameters from a standard 0.18 µm CMOS technology. Post-layout simulation shows that the center frequency of the filter is adjustable from 80 Hz to 6.18 kHz by using a programmable bias current generator. At a nominal center frequency of 945 Hz and the quality factor of 3, the filter exhibits a dynamic range of 57.6 dB and an input-referred noise of 174.2 µV. The filter consumes only 6 nW from a 1-V single Power Supply Voltage and the active area of the overall circuit is 0.088 mm^2.

  • a 1 v 6 nw programmable 4 th order bandpass filter for biomedical applications
    International New Circuits and Systems Conference, 2015
    Co-Authors: Yuwadee Sundarasaradula, Apinunt Thanachayanont
    Abstract:

    This paper presents the design and realization of a programmable 4th-order bandpass filter for biomedical applications in a standard 0.18 μm CMOS technology. The center frequency is adjustable from 80 Hz to 7 KHz, using a 6-bit digital-to-analog-converter (DAC). At a center frequency of 1 KHz and quality factor of 4, the simulated dynamic range is 53.6 dB for 1% total harmonic distortion (THD) and the simulated total input-referred noise, integrated from 875 Hz to 1.125 KHz, is 177μV. The filter consumes only 6 nW from a 1-V single Power Supply Voltage.

  • a low Voltage low Power wideband cmos variable gain amplifier using active negative feedback
    International Symposium on Intelligent Signal Processing and Communication Systems, 2009
    Co-Authors: Siraporn Sakphrom, Apinunt Thanachayanont, Phanumas Khumsat
    Abstract:

    This paper describes the design and realization of a low-Voltage low-Power RF variable gain amplifier in a 0.18um CMOS technology. The proposed amplifier employs an active negative feedback technique to achieve wide bandwidth operation. Simulation results showed that the proposed circuit could achieve 1.78-GHz bandwidth with 13.04-dB gain under a single 1-V Power Supply Voltage, while draining current less than 500 μA.

  • a microPower cmos preamplifier for cochlear implant system
    ITC-CSCC :International Technical Conference on Circuits Systems Computers and Communications, 2008
    Co-Authors: Apiradee Yodtean, Apinunt Thanachayanont
    Abstract:

    This paper proposes a CMOS low-Power low-Voltage microphone preamplifier for a cochlear implant system. The proposed preamplifier using the Flipped Voltage Follower Current Sensing (FVFCS) technique to achieve low Voltage, low Power consumption. The proposed circuit was designed and simulated using a 0.35㎛ CMOS process. Simulation results showed that the preamplifier can achieve 22-㏈ Voltage gain while dissipating only 5.2 ㎼ from 1.4-V Power Supply Voltage.

  • low Voltage current sensing cmos interface circuit for piezo resistive pressure sensor
    Etri Journal, 2007
    Co-Authors: Apinunt Thanachayanont, Suttisak Sangtong
    Abstract:

    A new low-Voltage CMOS interface circuit with digital output for piezo-resistive transducer is proposed. An input current sensing configuration is used to detect change in piezo-resistance due to applied pressure and to allow lowVoltage circuit operation. A simple 1-bit first-order deltasigma modulator is used to produce an output digital bitstream. The proposed interface circuit is realized in a 0. 35 µm CMOS technology and draws less than 200 μA from a single 1.5 V Power Supply Voltage. Simulation results show that the circuit can achieve an equivalent output resolution of 9.67 bits with less than 0.23% nonlinearity error.