The Experts below are selected from a list of 193170 Experts worldwide ranked by ideXlab platform
Ming-dou Ker - One of the best experts on this subject based on the ideXlab platform.
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esd Protection Design for 60 ghz lna with inductor triggered scr in 65 nm cmos process
IEEE Transactions on Microwave Theory and Techniques, 2012Co-Authors: Chunyu Lin, Liwei Chu, Ming-dou KerAbstract:To effectively protect the radio-frequency (RF) circuits in nanoscale CMOS technology from electrostatic discharge (ESD) damages, the silicon-controlled rectifier (SCR) devices have been used as main on-chip ESD Protection devices due to their high ESD robustness and low parasitic capacitance. In this paper, an SCR device assisted with an inductor is proposed to improve the turn-on efficiency for ESD Protection. Besides, the inductor can be also Designed to resonate with the parasitic capacitance of the SCR device at the selected frequency band for RF performance fine tuning. Experimental results of the ESD Protection Design with inductor-triggered SCR in a nanoscale CMOS process have been successfully verified at 60-GHz frequency. The ESD Protection Design with inductor-triggered SCR has been implemented in cell configuration with compact size, which can be directly used in the RF receiver circuits. To verify the RF characteristics and ESD robustness in the RF receiver, the inductor-triggered SCR has been applied to a 60-GHz low-noise amplifier (LNA). Verified in a silicon chip, the 60-GHz LNA with the inductor-triggered SCR can achieve good RF performances and high ESD robustness.
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cdm esd Protection Design with initial on concept in nanoscale cmos process
International Symposium on the Physical and Failure Analysis of Integrated Circuits, 2010Co-Authors: Chunyu Lin, Ming-dou KerAbstract:Integrated circuits (ICs) have been fabricated with thinner gate oxides to achieve higher speed and lower power consumption in nanoscale CMOS processes. However, the charged-device-model (CDM) electrostatic discharge (ESD) events became more critical because of the thinner gate oxide in nanoscale CMOS transistors and the larger die size for the system-on-chip (SoC) applications. Thus, effective on-chip ESD Protection Design against CDM ESD stresses has become more challenging to be implemented. A novel on-chip ESD Protection Design against CDM ESD events was proposed in this work, and its performance has been verified by the silicon chip fabricated in 55-nm CMOS process.
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On-Chip ESD Protection Design for Automotive Vacuum-Fluorescent-Display (VFD) Driver IC to Sustain High ESD Stress
IEEE Transactions on Device and Materials Reliability, 2007Co-Authors: Ming-dou Ker, Wei-jen ChangAbstract:A new electrostatic discharge (ESD) Protection structure of high-voltage p-type silicon-controlled rectifier (HVPSCR) that is embedded into a high-voltage p-channel MOS (HVPMOS) device is proposed to greatly improve the ESD robustness of the vacuum-fluorescent-display (VFD) driver IC for automotive electronics applications. By only adding the additional n+ diffusion into the drain region of HVPMOS, the transmission-line-pulsing-measured secondary breakdown current of the output driver has been greatly improved to be greater than 6 A in a 0.5- mum high-voltage complementary MOS process. Such ESD-enhanced VFD driver IC, which can sustain human-body-model ESD stress of up to 8 kV, has been in mass production for automotive applications in cars without the latchup problem. Moreover, with device widths of 500, 600, and 800 mum, the machine-model ESD levels of the HVPSCR are as high as 1100,1300, and 1900 V, respectively.
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overview of on chip electrostatic discharge Protection Design with scr based devices in cmos integrated circuits
IEEE Transactions on Device and Materials Reliability, 2005Co-Authors: Ming-dou Ker, Kuochun HsuAbstract:An overview on the electrostatic discharge (ESD) Protection circuits by using the silicon controlled rectifier (SCR)-based devices in CMOS ICs is presented. The history and evolution of SCR device used for on-chip ESD Protection is introduced. Moreover, two practical problems (higher switching voltage and transient-induced latchup issue) limiting the use of SCR-based devices in on-chip ESD Protection are reported. Some modified device structures and trigger-assist circuit techniques to reduce the switching voltage of SCR-based devices are discussed. The solutions to overcome latchup issue in the SCR-based devices are also discussed to safely apply the SCR-based devices for on-chip ESD Protection in CMOS IC products.
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esd Protection Design to overcome internal damage on interface circuits of a cmos ic with multiple separated power pins
IEEE Transactions on Components and Packaging Technologies, 2004Co-Authors: Ming-dou Ker, Chyh Yih Chang, Yishu ChangAbstract:This paper reports a real case of electrostatic discharge (ESD) improvement on a complementary metal oxide semiconductor integrated circuit (IC) product with multiple separated power pins. After ESD stresses, the internal damage have been found to locate at the interface circuit connecting between different circuit blocks with different power supplies. Some ESD Designs have been implemented to rescue this IC product to meet the required ESD specification. By adding only an extra ESD clamp N-channel metal oxide semiconductor with a channel width of 10 /spl mu/m between the interface node and the ground line, the human-body-model (HBM) ESD level of this IC product can be improved from the original 0.5 to 3 kV. By connecting the separated vertical sync signal (VSS) power lines through the ESD conduction circuit to a common VSS ESD bus realized by the seal ring, the HBM ESD level of the enhanced version IC product with 12 separated power supplies pairs can be significantly improved from original 1 kV up to > 5 kV, without the noise coupling issue.
Junggu Kim - One of the best experts on this subject based on the ideXlab platform.
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optimization of cathodic Protection Design for pre insulated pipeline in district heating system using computational simulation
Materials, 2019Co-Authors: Minsung Hong, Junggu KimAbstract:Cathodic Protection (CP) has been used as a primary method in the control of corrosion, therefore it is regarded as the most effective way for protecting buried pipelines. However, it is difficult to apply CP to a pipeline for district heating distribution systems, because the pipeline has thermally insulated coatings which could disturb the CP. Theoretical calculation and field tests alone are not enough for a reliable CP Design, and therefore additional CP Design methods such as computational analysis should be used. In this study, the CP Design for pre-insulated pipelines is tested considering several environmental factors, such as temperature and coating defect ratio. Additionally, computational analysis is performed to verify and optimize the CP Design. The simulation results based on theoretical methods alone failed to satisfy the CP criteria. Then, a re-Design is conducted considering the IR drop. Consequently, all of the simulation results of defective pipelines satisfied the CP criteria after adding the proper CP current.
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optimizing the sacrificial anode cathodic Protection of the rail canal structure in seawater using the boundary element method
Engineering Analysis With Boundary Elements, 2017Co-Authors: Yongsang Kim, Jeongguk Kim, Dooho Choi, Jaeyong Lim, Junggu KimAbstract:Abstract This paper deals with the cathodic Protection Design for axle/wheel and rail of ‘rail-canal system’ in the ocean. The cathodic Protection Design was carried out using the boundary element method and was verified by the physical miniature tests. The optimum cathodic Protection Designs were determined based on the cathodic potential distribution and anode lifetime provided by the simulation. The unprotected physical miniature experienced widespread corrosion, whereas the protected miniature was covered with calcareous deposit, indicating that the surface was fully protected from corrosion. This study demonstrated that the boundary element can be applicable to the cathodic Protection Design of rail-canal structure.
Albert Wang - One of the best experts on this subject based on the ideXlab platform.
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whole chip esd Protection Design verification by cad
2009 31st EOS ESD Symposium, 2009Co-Authors: Xin Wang, Rouying Zhan, Albert Wang, He Tang, Qiang Fang, Hui Zhao, Chai Ean Gill, Bin Zhao, Yumei Zhou, Gary ZhangAbstract:CAD is essential to simulation, Design and synthesis of on-chip ESD Protection circuitry to ensure Design prediction and verification at whole-chip level. This paper reviews a new function-based ESD CAD platform and Design methodology, including arbitrary ESD Protection device extraction algorithm, smart parametric ESD checking mechanism, smart ESD zapping simulation flow and new CAD tools enabling whole-chip ESD Protection Design verification. Practical Design examples are presented.
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esdzapper a new layout level verification tool for finding critical discharging path under esd stress
Asia and South Pacific Design Automation Conference, 2005Co-Authors: Rouying Zhan, Haigang Feng, Albert WangAbstract:On-chip ESD (electrostatic discharging) Protection is a challenging IC Design problem. New CAD tools are essential to ESD Protection Design prediction and verification at the full chip level. This paper reports a new CAD tool, entitled ESDZapper, to simulate the complex ESD Protection zapping test procedures and to find the critical discharging path under a specific ESD stress. ESDZapper is developed based on a novel concept of ESD-critical parameters. Capability of the new tool is demonstrated using a practical Design example in a 0.35/spl mu/m BiCMOS technology.
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a mixed mode esd Protection circuit simulation Design methodology
IEEE Journal of Solid-state Circuits, 2003Co-Authors: Haigang Feng, Guang Chen, Rouying Zhan, Xiaokang Guan, Haolu Xie, Albert Wang, R GafiteanuAbstract:On-chip electrostatic discharge (ESD) Protection Design becomes a major Design challenge as IC technologies continue to migrate into very-deep-submicron (VDSM) regime. However, trial-and-error approaches still dominate in ESD Protection circuit Design. This paper discusses a new mixed-mode ESD Protection simulation-Design methodology, aiming to Design prediction, which involves multiple-level coupling in ESD Protection simulation by solving complex electrothermal equations self-consistently at process, device, and circuit levels in a coupled fashion to investigate ESD Protection circuit details without any pre-assumption. Practical ESD Protection Design examples, implemented in commercial 0.18/0.35-/spl mu/m CMOS and BiCMOS processes, are presented.
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an on chip esd Protection circuit with low trigger voltage in bicmos technology
IEEE Journal of Solid-state Circuits, 2001Co-Authors: Albert Wang, Chenhui TsayAbstract:A novel low-trigger dual-direction on-chip electrostatic discharge (ESD) Protection circuit is Designed to protect integrated circuits (ICs) against ESD surges in two opposite directions. The compact ESD Protection circuit features low triggering voltage (/spl sim/7.5 V), short response time (0.18-0.4 ns), symmetric deep-snap-back I-V characteristics, and low on-resistance (/spl sim//spl Omega/). It passed the 14-kV human body model (HBM) ESD test and is very area efficient (/spl sim/80 V//spl mu/m width). The new ESD Protection Design is particularly suitable for low-voltage or multiple-power-supply IC chips.
Hansjoachim Bargstadt - One of the best experts on this subject based on the ideXlab platform.
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a case study on automated safety compliance checking to assist fall Protection Design and planning in building information models
Construction Management and Economics, 2013Co-Authors: Jurgen Melzner, Sijie Zhang, Jochen Teizer, Hansjoachim BargstadtAbstract:Worldwide occupational safety statistics show that the construction industry in many countries experiences one of the highest accident rates of all industry sectors. Falls remain a major concern as they contribute to very serious injuries or even fatalities on construction projects around the world. Since the standards and rules for protective safety equipment vary by country, the growing numbers of internationally operating companies are in need of tools that allow ubiquitous understanding and planning of safety regardless of the country where they operate. The problem is examined using a customizable automatic safety rule-checking platform for building information models. The applied rule-based checking algorithms are Designed to be add-ons to existing building information modelling (BIM) software and can check models for safety hazards early in the Design and planning process. Once hazards have been identified preventative safety equipment can be Designed, estimated, and included in the construction schedule before construction starts. A case study implements the safety rule-checking platform on a high-rise building project. Fall Protection regulations from both the USA and Germany are applied to the developed rule-checking platform. Visualization of the safety information further explains the differences in the results once country-specific safety-regulative standards are applied on the same building information model. The case study also indicates that the role of BIM in safety Design and planning can effectively assist the traditional safety decision-making process for fall Protection equipment.
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A case study on automated safety compliance checking to assist fall Protection Design and planning in building information models
Construction Management and Economics, 2013Co-Authors: Jurgen Melzner, Sijie Zhang, Jochen Teizer, Hansjoachim BargstadtAbstract:Worldwide occupational safety statistics show that the construction industry in many countries experiences one of the highest accident rates of all industry sectors. Falls remain a major concern as they contribute to very serious injuries or even fatalities on construction projects around the world. Since the standards and rules for protective safety equipment vary by country, the growing numbers of internationally operating companies are in need of tools that allow ubiquitous understanding and planning of safety regardless of the country where they operate. The problem is examined using a customizable automatic safety rule-checking platform for building information models. The applied rule-based checking algorithms are Designed to be add-ons to existing building information modelling (BIM) software and can check models for safety hazards early in the Design and planning process. Once hazards have been identified preventative safety equipment can be Designed, estimated, and included in the construction sc...
Rouying Zhan - One of the best experts on this subject based on the ideXlab platform.
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whole chip esd Protection Design verification by cad
2009 31st EOS ESD Symposium, 2009Co-Authors: Xin Wang, Rouying Zhan, Albert Wang, He Tang, Qiang Fang, Hui Zhao, Chai Ean Gill, Bin Zhao, Yumei Zhou, Gary ZhangAbstract:CAD is essential to simulation, Design and synthesis of on-chip ESD Protection circuitry to ensure Design prediction and verification at whole-chip level. This paper reviews a new function-based ESD CAD platform and Design methodology, including arbitrary ESD Protection device extraction algorithm, smart parametric ESD checking mechanism, smart ESD zapping simulation flow and new CAD tools enabling whole-chip ESD Protection Design verification. Practical Design examples are presented.
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esdzapper a new layout level verification tool for finding critical discharging path under esd stress
Asia and South Pacific Design Automation Conference, 2005Co-Authors: Rouying Zhan, Haigang Feng, Albert WangAbstract:On-chip ESD (electrostatic discharging) Protection is a challenging IC Design problem. New CAD tools are essential to ESD Protection Design prediction and verification at the full chip level. This paper reports a new CAD tool, entitled ESDZapper, to simulate the complex ESD Protection zapping test procedures and to find the critical discharging path under a specific ESD stress. ESDZapper is developed based on a novel concept of ESD-critical parameters. Capability of the new tool is demonstrated using a practical Design example in a 0.35/spl mu/m BiCMOS technology.
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a mixed mode esd Protection circuit simulation Design methodology
IEEE Journal of Solid-state Circuits, 2003Co-Authors: Haigang Feng, Guang Chen, Rouying Zhan, Xiaokang Guan, Haolu Xie, Albert Wang, R GafiteanuAbstract:On-chip electrostatic discharge (ESD) Protection Design becomes a major Design challenge as IC technologies continue to migrate into very-deep-submicron (VDSM) regime. However, trial-and-error approaches still dominate in ESD Protection circuit Design. This paper discusses a new mixed-mode ESD Protection simulation-Design methodology, aiming to Design prediction, which involves multiple-level coupling in ESD Protection simulation by solving complex electrothermal equations self-consistently at process, device, and circuit levels in a coupled fashion to investigate ESD Protection circuit details without any pre-assumption. Practical ESD Protection Design examples, implemented in commercial 0.18/0.35-/spl mu/m CMOS and BiCMOS processes, are presented.
