The Experts below are selected from a list of 321 Experts worldwide ranked by ideXlab platform

F. Maloberti - One of the best experts on this subject based on the ideXlab platform.

  • A 1 mV resolution 10 MS/s rail-to-rail comparator in 0.5 /spl mu/m low-voltage CMOS Digital Process
    1997 IEEE International Symposium on Circuits and Systems (ISCAS), 1997
    Co-Authors: R. Rivoir, F. Maloberti
    Abstract:

    A new comparator architecture for high-resolution, rail-to-rail comparison at high-speed and low power dissipation is presented. The internal structure of the comparator permits one to overcome the technological constraints arising from a purely Digital Process. In particular, no precision capacitors are needed in this design. The newly developed circuit consists of three different gain stages before a dynamic latch. The first stage achieves a rail-to-rail operation owing to two distinct amplifiers working in parallel. The two outputs are separately offset compensated and then connected to a differential difference amplifier (DDA). A third high-swing stage, preceding a current-limited dynamic latch, is used to ensure a fast regeneration time. Particular care has been taken to limit not only the static, but also the dynamic power dissipation of the Digital part. Circuit simulations on 0.5 /spl mu/m, 3.3 V single-supply CMOS Digital technology show that this architecture can easily achieve a 10 MS/s speed, at the expense of only 165 /spl mu/A typical static current consumption.

  • ALCD-analog libraries on CMOS Digital Process
    Proceedings of Third International Conference on Electronics Circuits and Systems, 1996
    Co-Authors: C. Dupuy, J.e. Franca, Azeredo C. Leme, F. Maloberti, R. Rivoir, G. Torelli, Y. Papananos
    Abstract:

    The main target of Esprit 8030 ALCD Project is to evaluate and demonstrate the effectiveness of the most up-to date CMOS Digital Process analog design techniques for developing industrial products. The development Process runs in two hierarchical steps: at the device level in WP3, library design, and at the system level in WP4, applications and demonstrators. About silicon characterization, advanced models-BSIM3-for a 0.5-/spl mu/m and two different 0.7-/spl mu/m CMOS Digital Processes have been validated, and "ad-hoc" special-purpose characterizations on some components have been also carried out. The developed analog library comprises more than thirty analog cells. Several of them have already been characterized, others have been qualified and embedded into cell-based commercial ASICs (CBICs) products. Some analog functions (ADC, DAC, Sigma-Delta modulators, Filters), have been implemented by using different design techniques, in order to find optimum solutions. The silicon of the two industrial demonstrators will be ready in September 1996.

  • Power consumption optimization of 8 bit, 2 MHz voltage scaling subranging CMOS 0.5 /spl mu/m DAC
    Proceedings of Third International Conference on Electronics Circuits and Systems, 1996
    Co-Authors: F. Maloberti, R. Rivoir, G. Torelli
    Abstract:

    We present the design of an 8-bit voltage-scaling, subranging Digital-to-analog converter with a current-biased floating fine ladder. The basic structure has been analyzed and optimized for the best trade-off between conversion speed and power dissipation. This allowed us to design a 4+4 bit converter capable to drive 4 pF with 200 /spl mu/A current consumption running at 2 MHz. Circuit simulations on a 0.5 /spl mu/m, 3.3 V single-supply CMOS Digital Process show that the above performances are fully achieved even in worst-case Process conditions.

  • Design of a voltage-to-current converting interface for current-mode video signal Processing applications
    1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings, 1996
    Co-Authors: F. Maloberti, R. Rivoir
    Abstract:

    Voltage-to-current converters (VICs) are starting to be extensively used in video speed current-mode analog circuits, especially in A/D converters, as internal building blocks or external interfaces with voltage-mode signals. Despite the important role played by VIC's in video signal Processing systems, until now no design examples nor experimental results on video rate VIC's have been reported. The purpose of this paper is to present the design of a newly developed VI converter, suitable for interfacing 8-b current-mode circuits operating at video frequencies with voltage signals. A test circuit has been fabricated in 0.7-/spl mu/m, 5-V single-supply CMOS Digital Process.

R. Suszynski - One of the best experts on this subject based on the ideXlab platform.

  • Experimental circuit with current mode /spl Sigma//spl Delta/ modulators with switched transconductance
    ICECS 2000. 7th IEEE International Conference on Electronics Circuits and Systems (Cat. No.00EX445), 2000
    Co-Authors: R. Suszynski
    Abstract:

    This paper presents measuring and experimental results of A/D converters with current mode /spl Sigma//spl Delta/ modulators. The /spl Sigma//spl Delta/ modulator structures are composed of current mode blocks with transconductance amplifiers and their parasitic input capacitances. /spl Sigma//spl Delta/ modulator structures were designed and simulated by using VLSISPICE COMPASS DESIGN program and finally designed by using UNCLE program and then manufactured via Eurochip service center in 0.7 /spl mu/m ES2 Digital Process to verify proposed concept. Three different /spl Sigma//spl Delta/ structures: first-order, second-order and multistage third-order were measured and results are shown in the paper.

  • Measuring and experimental results of current mode /spl Sigma//spl Delta/ modulators with switched transconductance
    ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics Circuits and Systems (Cat. No.99EX357), 1999
    Co-Authors: R. Suszynski
    Abstract:

    This paper presents measuring and experimental results of A/D converters with current mode /spl Sigma//spl Delta/ modulators. The /spl Sigma//spl Delta/ modulator structures are composed of current mode blocks with transconductance amplifiers and their parasitic input capacitances. /spl Sigma//spl Delta/ modulator structures were designed and simulated by using the VLSISPICE COMPASS DESIGN program and finally designed by using the UNCLE program and then manufactured via Eurochip service center in a 0.7 /spl mu/m ES2 Digital Process to verify the proposed concept. Three different /spl Sigma//spl Delta/ structures: first-order, second-order and multistage third-order were measured and results are given in the paper.

C. Toumazou - One of the best experts on this subject based on the ideXlab platform.

  • Switched current circuit design techniques for single-bit, high speed sigma-delta modulators
    IEE Colloquium on Oversampling Techniques and Sigma-Delta Modulation, 1994
    Co-Authors: C. Toumazou, G. Saether, M. Adams
    Abstract:

    This paper reviews some research aimed at developing suitable circuit techniques to implement high speed Sigma Delta modulators on a pure Digital Process technology. Techniques are presented in both Si and GaAs technologies, and in both instances performance is optimised for speed. Simulations presented for the Si circuits employ MOSFETs from the 0.8 mu m Northern Telecom BiCMOS technology.

  • Towards high frequency switched-current filters in CMOS and GaAs technology
    1993 IEEE International Symposium on Circuits and Systems (ISCAS), 1993
    Co-Authors: N.c. Battersby, C. Toumazou
    Abstract:

    The switched-current technique is a relatively new analog sampled-data signal Processing technique which aims at replacing switched capacitors by offering superior Digital Process compatibility and the potential for higher operating frequencies. The high frequency potential of switched-currents is explored by showing an integrated fifth-order bilinear elliptic filter, operating at a maximum clock frequency of 5.75 MHz, and the first implementation of switched currents in GaAs MESFET technology, with a simulated clock frequency of 1 GHz.

R. Rivoir - One of the best experts on this subject based on the ideXlab platform.

  • A 1 mV resolution 10 MS/s rail-to-rail comparator in 0.5 /spl mu/m low-voltage CMOS Digital Process
    1997 IEEE International Symposium on Circuits and Systems (ISCAS), 1997
    Co-Authors: R. Rivoir, F. Maloberti
    Abstract:

    A new comparator architecture for high-resolution, rail-to-rail comparison at high-speed and low power dissipation is presented. The internal structure of the comparator permits one to overcome the technological constraints arising from a purely Digital Process. In particular, no precision capacitors are needed in this design. The newly developed circuit consists of three different gain stages before a dynamic latch. The first stage achieves a rail-to-rail operation owing to two distinct amplifiers working in parallel. The two outputs are separately offset compensated and then connected to a differential difference amplifier (DDA). A third high-swing stage, preceding a current-limited dynamic latch, is used to ensure a fast regeneration time. Particular care has been taken to limit not only the static, but also the dynamic power dissipation of the Digital part. Circuit simulations on 0.5 /spl mu/m, 3.3 V single-supply CMOS Digital technology show that this architecture can easily achieve a 10 MS/s speed, at the expense of only 165 /spl mu/A typical static current consumption.

  • ALCD-analog libraries on CMOS Digital Process
    Proceedings of Third International Conference on Electronics Circuits and Systems, 1996
    Co-Authors: C. Dupuy, J.e. Franca, Azeredo C. Leme, F. Maloberti, R. Rivoir, G. Torelli, Y. Papananos
    Abstract:

    The main target of Esprit 8030 ALCD Project is to evaluate and demonstrate the effectiveness of the most up-to date CMOS Digital Process analog design techniques for developing industrial products. The development Process runs in two hierarchical steps: at the device level in WP3, library design, and at the system level in WP4, applications and demonstrators. About silicon characterization, advanced models-BSIM3-for a 0.5-/spl mu/m and two different 0.7-/spl mu/m CMOS Digital Processes have been validated, and "ad-hoc" special-purpose characterizations on some components have been also carried out. The developed analog library comprises more than thirty analog cells. Several of them have already been characterized, others have been qualified and embedded into cell-based commercial ASICs (CBICs) products. Some analog functions (ADC, DAC, Sigma-Delta modulators, Filters), have been implemented by using different design techniques, in order to find optimum solutions. The silicon of the two industrial demonstrators will be ready in September 1996.

  • Power consumption optimization of 8 bit, 2 MHz voltage scaling subranging CMOS 0.5 /spl mu/m DAC
    Proceedings of Third International Conference on Electronics Circuits and Systems, 1996
    Co-Authors: F. Maloberti, R. Rivoir, G. Torelli
    Abstract:

    We present the design of an 8-bit voltage-scaling, subranging Digital-to-analog converter with a current-biased floating fine ladder. The basic structure has been analyzed and optimized for the best trade-off between conversion speed and power dissipation. This allowed us to design a 4+4 bit converter capable to drive 4 pF with 200 /spl mu/A current consumption running at 2 MHz. Circuit simulations on a 0.5 /spl mu/m, 3.3 V single-supply CMOS Digital Process show that the above performances are fully achieved even in worst-case Process conditions.

  • Design of a voltage-to-current converting interface for current-mode video signal Processing applications
    1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings, 1996
    Co-Authors: F. Maloberti, R. Rivoir
    Abstract:

    Voltage-to-current converters (VICs) are starting to be extensively used in video speed current-mode analog circuits, especially in A/D converters, as internal building blocks or external interfaces with voltage-mode signals. Despite the important role played by VIC's in video signal Processing systems, until now no design examples nor experimental results on video rate VIC's have been reported. The purpose of this paper is to present the design of a newly developed VI converter, suitable for interfacing 8-b current-mode circuits operating at video frequencies with voltage signals. A test circuit has been fabricated in 0.7-/spl mu/m, 5-V single-supply CMOS Digital Process.

Antti Makitie - One of the best experts on this subject based on the ideXlab platform.

  • a Digital Process for additive manufacturing of occlusal splints a clinical pilot study
    Journal of the Royal Society Interface, 2013
    Co-Authors: Mika Salmi, Kaijastiina Paloheimo, Jukka Tuomi, Tuula Ingman, Antti Makitie
    Abstract:

    The aim of this study was to develop and evaluate a Digital Process for manufacturing of occlusal splints. An alginate impression was taken from the upper and lower jaws of a patient with temporomandibular disorder owing to cross bite and wear of the teeth, and then digitized using a table laser scanner. The scanned model was repaired using the 3Data Expert software, and a splint was designed with the Viscam RP software. A splint was manufactured from a biocompatible liquid photopolymer by stereolithography. The system employed in the Process was SLA 350. The splint was worn nightly for six months. The patient adapted to the splint well and found it comfortable to use. The splint relieved tension in the patient's bite muscles. No sign of tooth wear or significant splint wear was detected after six months of testing. Modern Digital technology enables us to manufacture clinically functional occlusal splints, which might reduce costs, dental technician working time and chair-side time. Maximum-dimensional errors of approximately 1 mm were found at thin walls and sharp corners of the splint when compared with the Digital model.